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XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
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Product Description * Complete Development System - Schematic capture, automatic place and route - Logic and timing simulation - Interactive design editor for design optimization - Timing calculator - Interfaces to popular design environments like Viewlogic, Cadence, Mentor Graphics, and others
Features
* Complete line of four related Field Programmable Gate Array product families - XC3000A, XC3000L, XC3100A, XC3100L Ideal for a wide range of custom VLSI design tasks - Replaces TTL, MSI, and other PLD logic - Integrates complete sub-systems into a single package - Avoids the NRE, time delay, and risk of conventional masked gate arrays High-performance CMOS static memory technology - Guaranteed toggle rates of 70 to 370 MHz, logic delays from 7 to 1.5 ns - System clock speeds over 85 MHz - Low quiescent and active power consumption Flexible FPGA architecture - Compatible arrays ranging from 1,000 to 7,500 gate complexity - Extensive register, combinatorial, and I/O capabilities - High fan-out signal distribution, low-skew clock nets - Internal 3-state bus capabilities - TTL or CMOS input thresholds - On-chip crystal oscillator amplifier Unlimited reprogrammability - Easy design iteration - In-system logic changes Extensive packaging options - Over 20 different packages - Plastic and ceramic surface-mount and pin-gridarray packages - Thin and Very Thin Quad Flat Pack (TQFP and VQFP) options Ready for volume production - Standard, off-the-shelf product availability - 100% factory pre-tested devices - Excellent reliability record
Device XC3020A, 3020L, 3120A XC3030A, 3030L, 3130A XC3042A, 3042L, 3142A, 3142L XC3064A, 3064L, 3164A XC3090A, 3090L, 3190A, 3190L XC3195A Max Logic Gates 1,500 2,000 3,000 4,500 6,000 7,500 Typical Gate CLBs Range 1,000 - 1,500 64 1,500 - 2,000 2,000 - 3,000 3,500 - 4,500 5,000 - 6,000 6,500 - 7,500 100 144 224 320 484
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Additional XC3100A Features
* Ultra-high-speed FPGA family with six members - 50-85 MHz system clock rates - 190 to 370 MHz guaranteed flip-flop toggle rates - 1.55 to 4.1 ns logic delays High-end additional family member in the 22 X 22 CLB array-size XC3195A device 8 mA output sink current and 8 mA source current Maximum power-down and quiescent current is 5 mA 100% architecture and pin-out compatible with other XC3000 families Software and bitstream compatible with the XC3000, XC3000A, and XC3000L families
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XC3100A combines the features of the XC3000A and XC3100 families: * * * * Additional interconnect resources for TBUFs and CE inputs Error checking of the configuration bitstream Soft startup holds all outputs slew-rate limited during initial power-up More advanced CMOS process
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Low-Voltage Versions Available
* * * Low-voltage devices function at 3.0 - 3.6 V XC3000L - Low-voltage versions of XC3000A devices XC3100L - Low-voltage versions of XC3100A devices
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Array 8x8 10 x 10 12 x 12 16 x 14 16 x 20 22 x 22
User I/Os Flip-Flops Max 64 256 80 96 120 144 176 360 480 688 928 1,320
Horizontal Longlines 16 20 24 32 40 44
Configuration Data Bits 14,779 22,176 30,784 46,064 64,160 94,984
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Introduction
XC3000-Series Field Programmable Gate Arrays (FPGAs) provide a group of high-performance, high-density, digital integrated circuits. Their regular, extendable, flexible, user-programmable array architecture is composed of a configuration program store plus three types of configurable elements: a perimeter of I/O Blocks (IOBs), a core array of Configurable Logic Bocks (CLBs) and resources for interconnection. The general structure of an FPGA is shown in Figure 2. The development system provides schematic capture and auto place-and-route for design entry. Logic and timing simulation, and in-circuit emulation are available as design verification alternatives. The design editor is used for interactive design optimization, and to compile the data pattern that represents the configuration program. The FPGA user logic functions and interconnections are determined by the configuration program data stored in internal static memory cells. The program can be loaded in any of several modes to accommodate various system requirements. The program data resides externally in an EEPROM, EPROM or ROM on the application circuit board, or on a floppy disk or hard disk. On-chip initialization logic provides for optional automatic loading of program data at power-up. The companion XC17XX Serial Configuration PROMs provide a very simple serial configuration program storage in a one-time programmable package. The XC3000 Field Programmable Gate Array families provide a variety of logic capacities, package styles, temperature ranges and speed grades.
Here is a simple overview of those XC3000 products currently emphasized: * XC3000A Family -- The XC3000A is an enhanced version of the basic XC3000 family, featuring additional interconnect resources and other user-friendly enhancements. XC3000L Family -- The XC3000L is identical in architecture and features to the XC3000A family, but operates at a nominal supply voltage of 3.3 V. The XC3000L is the right solution for battery-operated and low-power applications. XC3100A Family -- The XC3100A is a performance-optimized relative of the XC3000A family. While both families are bitstream and footprint compatible, the XC3100A family extends toggle rates to 370 MHz and in-system performance to over 80 MHz. The XC3100A family also offers one additional array size, the XC3195A. XC3100L Family -- The XC3100L is identical in architectures and features to the XC3100A family, but operates at a nominal supply voltage of 3.3V.
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Figure 1 illustrates the relationships between the families. Compared to the original XC3000 family, XC3000A offers additional functionality and increased speed. The XC3000L family offers the same additional functionality, but reduced speed due to its lower supply voltage of 3.3 V. The XC3100A family offers substantially higher speed and higher density with the XC3195A.
New XC3000 Series Compared to Original XC3000 Family
For readers already familiar with the original XC3000 family of FPGAs, the major new features in the XC3000A, XC3000L, XC3100A, and XC3100L families are listed in this section. All of these new families are upward-compatible extensions of the original XC3000 FPGA architecture. Any bitstream used to configure an XC3000 device will configure the corresponding XC3000A, XC3000L, XC3100A, or XC3100L device exactly the same way. The XC3100A and XC3100L FPGA architectures are upward-compatible extensions of the XC3000A and XC3000L architectures. Any bitstream used to configure an XC3000A or XC3000L device will configure the corresponding XC3100A or XC3100L device exactly the same way.
XC3000 Series Overview
There are now four distinct family groupings within the XC3000 Series of FPGA devices: * * * * XC3000A Family XC3000L Family XC3100A Family XC3100L Family
All four families share a common architecture, development software, design and programming methodology, and also common package pin-outs. An extensive Product Description covers these common aspects. Detailed parametric information for the XC3000A, XC3000L, XC3100A, and XC3100L product families is then provided. (The XC3000 and XC3100 families are not recommended for new designs.)
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Improvements in the XC3000A and XC3000L Families
The XC3000A and XC3000L families offer the following enhancements over the popular XC3000 family: The XC3000A and XC3000L families have additional interconnect resources to drive the I-inputs of TBUFs driving horizontal Longlines. The CLB Clock Enable input can be driven from a second vertical Longline. These two additions result in more efficient and faster designs when horizontal Longlines are used for data bussing. During configuration, the XC3000A and XC3000L devices check the bit-stream format for stop bits in the appropriate positions. Any error terminates the configuration and pulls INIT Low. When the configuration process is finished and the device starts up in user mode, the first activation of the outputs is automatically slew-rate limited. This feature, called Soft Startup, avoids the potential ground bounce when all out-puts are turned on simultaneously. After start-up, the slew rate of the individual outputs is, as in the XC3000 family, determined by the individual configuration option.
(XC3 195A )
Functio
nality
XC310 00L 0 XC310XC31 XC300 0L XC300 0A
0A
Speed
city Capa Gate
X7068
Figure 1: XC3000 FPGA Families
Improvements in the XC3100A and XC3100L Families
Based on a more advanced CMOS process, the XC3100A and XC3100L families are architecturally-identical, performance-optimized relatives of the XC3000A and XC3000L families. While all families are footprint compatible, the XC3100A family extends achievable system performance beyond 85 MHz.
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Detailed Functional Description
The perimeter of configurable Input/Output Blocks (IOBs) provides a programmable interface between the internal logic array and the device package pins. The array of Configurable Logic Blocks (CLBs) performs user-specified logic functions. The interconnect resources are programmed to form networks, carrying logic signals among blocks, analogous to printed circuit board traces connecting MSI/SSI packages. The block logic functions are implemented by programmed look-up tables. Functional options are implemented by program-controlled multiplexers. Interconnecting networks between blocks are implemented with metal segments joined by program-controlled pass transistors. These FPGA functions are established by a configuration program which is loaded into an internal, distributed array of configuration memory cells. The configuration program is loaded into the device at power-up and may be reloaded on command. The FPGA includes logic and control signals to implement automatic or passive configuration. Program data may be either bit serial or byte parallel. The development system generates the configuration program bitstream used to configure the device. The memory loading process is independent of the user logic functions.
Configuration Memory
The static memory cell used for the configuration memory in the Field Programmable Gate Array has been designed specifically for high reliability and noise immunity. Integrity of the device configuration memory based on this design is assured even under adverse conditions. As shown in Figure 3, the basic memory cell consists of two CMOS inverters plus a pass transistor used for writing and reading cell data. The cell is only written during configuration and only read during readback. During normal operation, the cell provides continuous control and the pass transistor is off and does not affect cell stability. This is quite different from the operation of conventional memory devices, in which the cells are frequently read and rewritten.
PWR DN
P9
P8
P7
P6
P5
P4
P3
P2
GND
I/O Blocks
P11
3-State Buffers With Access to Horizontal Long Lines
Configurable Logic Blocks
TCL KIN AA P12 AB AC AD
Interconnect Area
P13 BA U61 BB
Configuration Memory
X3241
Figure 2: Field Programmable Gate Array Structure. It consists of a perimeter of programmable I/O blocks, a core of configurable logic blocks and their interconnect resources. These are all controlled by the distributed array of configuration program memory cells.
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testing, no soft errors have been observed even in the presence of very high doses of alpha radiation.
Configuration Control
Q Read or Write Data Q
X5382
Figure 3: Static Configuration Memory Cell. It is loaded with one bit of configuration program and controls one program selection in the Field Programmable Gate Array.
The method of loading the configuration data is selectable. Two methods use serial data, while three use byte-wide data. The internal configuration logic utilizes framing information, embedded in the program data by the development system, to direct memory-cell loading. The serial-data framing and length-count preamble provide programming compatibility for mixes of various FPGA device devices in a synchronous, serial, daisy-chain fashion.
I/O Block
Each user-configurable IOB shown in Figure 4, provides an interface between the external package pin of the device and the internal user logic. Each IOB includes both registered and direct input paths. Each IOB provides a programmable 3-state output buffer, which may be driven by a registered or direct output signal. Configuration options allow each IOB an inversion, a controlled slew rate and a high impedance pull-up. Each input circuit also provides input clamping diodes to provide electrostatic protection, and circuits to inhibit latch-up produced by input currents.
Vcc
The memory cell outputs Q and Q use ground and VCC levels and provide continuous, direct control. The additional capacitive load together with the absence of address decoding and sense amplifiers provide high stability to the cell. Due to the structure of the configuration memory cells, they are not affected by extreme power-supply excursions or very high levels of alpha particle radiation. In reliability
PROGRAM-CONTROLLED MEMORY CELLS
OUT INVERT
3-STATE INVERT
OUTPUT SELECT
SLEW RATE
PASSIVE PULL UP
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3- STATE (OUTPUT ENABLE)
T
OUT
O
D
Q
FLIP FLOP
OUTPUT BUFFER
I/O PAD R DIRECT IN REGISTERED IN I Q Q D FLIP FLOP or LATCH R OK IK (GLOBAL RESET) TTL or CMOS INPUT THRESHOLD
CK1
CK2 PROGRAM CONTROLLED MULTIPLEXER = PROGRAMMABLE INTERCONNECTION POINT or PIP
X3029
Figure 4: Input/Output Block. Each IOB includes input and output storage elements and I/O options selected by configuration memory cells. A choice of two clocks is available on each die edge. The polarity of each clock line (not each flip-flop or latch) is programmable. A clock line that triggers the flip-flop on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice versa. Passive pull-up can only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS thresholds.
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The input-buffer portion of each IOB provides threshold detection to translate external signals applied to the package pin to internal logic levels. The global input-buffer threshold of the IOBs can be programmed to be compatible with either TTL or CMOS levels. The buffered input signal drives the data input of a storage element, which may be configured as either a flip-flop or a latch. The clocking polarity (rising/falling edge-triggered flip-flop, High/Low transparent latch) is programmable for each of the two clock lines on each of the four die edges. Note that a clock line driving a rising edge-triggered flip-flop makes any latch driven by the same line on the same edge Low-level transparent and vice versa (falling edge, High transparent). All Xilinx primitives in the supported schematic-entry packages, however, are positive edge-triggered flip-flops or High transparent latches. When one clock line must drive flip-flops as well as latches, it is necessary to compensate for the difference in clocking polarities with an additional inverter either in the flip-flop clock input or the latch-enable input. I/O storage elements are reset during configuration or by the active-Low chip RESET input. Both direct input (from IOB pin I) and registered input (from IOB pin Q) signals are available for interconnect. For reliable operation, inputs should have transition times of less than 100 ns and should not be left floating. Floating CMOS input-pin circuits might be at threshold and produce oscillations. This can produce additional power dissipation and system noise. A typical hysteresis of about 300 mV reduces sensitivity to input noise. Each user IOB includes a programmable high-impedance pull-up resistor, which may be selected by the program to provide a constant High for otherwise undriven package pins. Although the Field Programmable Gate Array provides circuitry to provide input protection for electrostatic discharge, normal CMOS handling precautions should be observed. Flip-flop loop delays for the IOB and logic-block flip-flops are short, providing good performance under asynchronous clock and data conditions. Short loop delays minimize the probability of a metastable condition that can result from assertion of the clock during data transitions. Because of the short-loop-delay characteristic in the Field Programmable Gate Array, the IOB flip-flops can be used to synchronize external signals applied to the device. Once synchronized in the IOB, the signals can be used internally without further consideration of their clock relative timing, except as it applies to the internal logic and routing-path delays. IOB output buffers provide CMOS-compatible 4-mA source-or-sink drive for high fan-out CMOS or TTL- compatible signal levels (8 mA in the XC3100A family). The network driving IOB pin O becomes the registered or direct data source for the output buffer. The 3-state control signal (IOB) pin T can control output activity. An open-drain output may be obtained by using the same signal for driving the output and 3-state signal nets so that the buffer output is enabled only for a Low. Configuration program bits for each IOB control features such as optional output register, logic signal inversion, and 3-state and slew-rate control of the output. The program-controlled memory cells of Figure 4 control the following options. * * Logic inversion of the output is controlled by one configuration program bit per IOB. Logic 3-state control of each IOB output buffer is determined by the states of configuration program bits that turn the buffer on, or off, or select the output buffer 3-state control interconnection (IOB pin T). When this IOB output control signal is High, a logic one, the buffer is disabled and the package pin is high impedance. When this IOB output control signal is Low, a logic zero, the buffer is enabled and the package pin is active. Inversion of the buffer 3-state control-logic sense (output enable) is controlled by an additional configuration program bit. Direct or registered output is selectable for each IOB. The register uses a positive-edge, clocked flip-flop. The clock source may be supplied (IOB pin OK) by either of two metal lines available along each die edge. Each of these lines is driven by an invertible buffer. Increased output transition speed can be selected to improve critical timing. Slower transitions reduce capacitive-load peak currents of non-critical outputs and minimize system noise. An internal high-impedance pull-up resistor (active by default) prevents unconnected inputs from floating.
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Unlike the original XC3000 series, the XC3000A, XC3000L, XC3100A, and XC3100L families include the Soft Startup feature. When the configuration process is finished and the device starts up in user mode, the first activation of the outputs is automatically slew-rate limited. This feature avoids potential ground bounce when all outputs are turned on simultaneously. After start-up, the slew rate of the individual outputs is determined by the individual configuration option.
Summary of I/O Options
* Inputs - Direct - Flip-flop/latch - CMOS/TTL threshold (chip inputs) - Pull-up resistor/open circuit Outputs - Direct/registered - Inverted/not - 3-state/on/off - Full speed/slew limited - 3-state/output enable (inverse)
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XC3000 Series Field Programmable Gate Arrays Configurable Logic Block
The array of CLBs provides the functional elements from which the user's logic is constructed. The logic blocks are arranged in a matrix within the perimeter of IOBs. For example, the XC3020A has 64 such blocks arranged in 8 rows and 8 columns. The development system is used to compile the configuration data which is to be loaded into the internal configuration memory to define the operation and interconnection of each block. User definition of CLBs and their interconnecting networks may be done by automatic translation from a schematic-capture logic diagram or optionally by installing library or user macros. Each CLB has a combinatorial logic section, two flip-flops, and an internal control section. See Figure 5. There are: five logic inputs (A, B, C, D and E); a common clock input (K); an asynchronous direct RESET input (RD); and an enable clock (EC). All may be driven from the interconnect resources adjacent to the blocks. Each CLB also has two outputs (X and Y) which may drive interconnect networks. Data input for either flip-flop within a CLB is supplied from the function F or G outputs of the combinatorial logic, or the block input, DI. Both flip-flops in each CLB share the asynchronous RD which, when enabled and High, is dominant over clocked inputs. All flip-flops are reset by the active-Low chip input, RESET, or during the configuration process. The flip-flops share the enable clock (EC) which, when Low, recirculates the flip-flops' present states and inhibits response to the data-in or combinatorial function inputs on a CLB. The user may enable these control inputs and select their sources. The user may also select the clock net input (K), as well as its active sense within each CLB. This programmable inversion eliminates the need to route both phases of a clock signal throughout the device.
DI DATA IN 0 MUX F DIN G RD QX A B LOGIC VARIABLES C D E QY F DIN G 0 MUX 1 D Q QY COMBINATORIAL FUNCTION G G Y CLB OUTPUTS F F QX X 1 D Q
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EC ENABLE CLOCK 1 (ENABLE) RD
K CLOCK
DIRECT RESET
RD
0 (INHIBIT) (GLOBAL RESET)
X3032
Figure 5: Configurable Logic Block. Each CLB includes a combinatorial logic section, two flip-flops and a program memory controlled multiplexer selection of function. It has the following: - five logic variable inputs A, B, C, D, and E - a direct data in DI - an enable clock EC - a clock (invertible) K - an asynchronous direct RESET RD - two outputs X and Y
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Flexible routing allows use of common or individual CLB clocking. The combinatorial-logic portion of the CLB uses a 32 by 1 look-up table to implement Boolean functions. Variables selected from the five logic inputs and two internal block flip-flops are used as table address inputs. The combinatorial propagation delay through the network is independent of the logic function generated and is spike free for single input variable changes. This technique can generate two independent logic functions of up to four variables each as shown in Figure 6a, or a single function of five variables as shown in Figure 6b, or some functions of seven variables as shown in Figure 6c. Figure 7 shows a modulo-8 binary counter with parallel enable. It uses one CLB of each type. The partial functions of six or seven variables are implemented using the input variable (E) to dynamically select between two functions of four different variables. For the two functions of four variables each, the independent results (F and G) may be used as data inputs to either flip-flop or either logic block output. For the single function of five variables and merged functions of six or seven variables, the F and G outputs are identical. Symmetry of the F and G functions and the flip-flops allows the interchange of CLB outputs to optimize routing efficiencies of the networks interconnecting the CLBs and IOBs.
A B QX QY C D E A B QX QY C D E Any Function of Up to 4 Variables G Any Function of Up to 4 Variables F
5a
A B QX QY C D E Any Function of 5 Variables G F
5b
A B QX Any Function of Up to 4 Variables F M U X QX QY C D E 5c FGM Mode
X5442
Programmable Interconnect
Programmable-interconnection resources in the Field Programmable Gate Array provide routing paths to connect inputs and outputs of the IOBs and CLBs into logic networks. Interconnections between blocks are composed of a two-layer grid of metal segments. Specially designed pass transistors, each controlled by a configuration bit, form programmable interconnect points (PIPs) and switching matrices used to implement the necessary connections between selected metal segments and block pins. Figure 8 is an example of a routed net. The development system provides automatic routing of these interconnections. Interactive routing is also available for design optimization. The inputs of the CLBs or IOBs are multiplexers which can be programmed to select an input network from the adjacent interconnect segments. Since the switch connections to block inputs are unidirectional, as are block outputs, they are usable only for block input connection and not for routing. Figure 9 illustrates routing access to logic block input variables, control inputs and block outputs. Three types of metal resources are provided to accommodate various network interconnect requirements. * * * General Purpose Interconnect Direct Connection Longlines (multiplexed busses and wide AND gates)
C D
QY
A B Any Function of Up to 4 Variables
G
Figure 6: Combinational Logic Options 6a. Combinatorial Logic Option FG generates two functions of four variables each. One variable, A, must be common to both functions. The second and third variable can be any choice of B, C, QX and QY. The fourth variable can be any choice of D or E. 6b. Combinatorial Logic Option F generates any function of five variables: A, D, E and two choices out of B, C, QX, QY. 6c. Combinatorial Logic Option FGM allows variable E to select between two functions of four variables: Both have common inputs A and D and any choice out of B, C, QX and QY for the remaining two variables. Option 3 can then implement some functions of six or seven variables.
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Count Enable Parallel Enable Clock
Terminal Count
Dual Function of 4 Variables
D D0
Q
Q0
FG Mode
D D1 Function of 5 Variables
Q
Q1
F Mode
D D2
Q
Q2
Function of 6 Variables FGM Mode
X5383
Figure 8: A Design Editor view of routing resources used to form a typical interconnection network from CLB GA. and to the right. The other PIPs adjacent to the matrices are accessed to or from Longlines. The development system automatically defines the buffer direction based on the location of the interconnection network source. The delay calculator of the development system automatically calculates and displays the block, interconnect and buffer delays for any paths selected. Generation of the simulation netlist with a worst-case delay model is provided.
Figure 7: Counter. The modulo-8 binary counter with parallel enable and clock enable uses one combinatorial logic block of each option.
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General Purpose Interconnect
General purpose interconnect, as shown in Figure 10, consists of a grid of five horizontal and five vertical metal segments located between the rows and columns of logic and IOBs. Each segment is the height or width of a logic block. Switching matrices join the ends of these segments and allow programmed interconnections between the metal grid segments of adjoining rows and columns. The switches of an unprogrammed device are all non-conducting. The connections through the switch matrix may be established by the automatic routing or by selecting the desired pairs of matrix pins to be connected or disconnected. The legitimate switching matrix combinations for each pin are indicated in Figure 11. Special buffers within the general interconnect areas provide periodic signal isolation and restoration for improved performance of lengthy nets. The interconnect buffers are available to propagate signals in either direction on a given general interconnect segment. These bidirectional (bidi) buffers are found adjacent to the switching matrices, above
Direct Interconnect
Direct interconnect, shown in Figure 12, provides the most efficient implementation of networks between adjacent CLBs or I/O Blocks. Signals routed from block to block using the direct interconnect exhibit minimum interconnect propagation and use no general interconnect resources. For each CLB, the X output may be connected directly to the B input of the CLB immediately to its right and to the C input of the CLB to its left. The Y output can use direct interconnect to drive the D input of the block immediately above and the A input of the block below. Direct interconnect should be used to maximize the speed of high-performance portions of logic. Where logic blocks are adjacent to IOBs, direct connect is provided alternately to the IOB inputs (I) and outputs (O) on all four edges of the die. The right edge provides additional direct connects from CLB outputs to adjacent IOBs. Direct interconnections of IOBs with CLBs are shown in Figure 13.
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Figure 9: Design Editor Locations of interconnect access, CLB control inputs, logic inputs and outputs. The dot pattern represents the available programmable interconnection points (PIPs). Some of the interconnect PIPs are directional.
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Figure 10: FPGA General-Purpose Interconnect. Composed of a grid of metal segments that may be interconnected through switch matrices to form networks for CLB and IOB inputs and outputs.
Figure 12: CLB X and Y Outputs. The X and Y outputs of each CLB have single contact, direct access to inputs of adjacent CLBs
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Figure 11: Switch Matrix Interconnection Options for Each Pin. Switch matrices on the edges are different.
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Global Buffer Direct Input
Global Buffer Inerconnect
* Unbonded IOBs (6 Places)
Figure 13:
Alternate Buffer Direct Input
XC3020A Die-Edge IOBs. The XC3020A die-edge IOBs are provided with direct access to adjacent CLBs.
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Longlines
The Longlines bypass the switch matrices and are intended primarily for signals that must travel a long distance, or must have minimum skew among multiple destinations. Longlines, shown in Figure 14, run vertically and horizontally the height or width of the interconnect area. Each interconnection column has three vertical Longlines, and each interconnection row has two horizontal Longlines. Two additional Longlines are located adjacent to the outer sets of switching matrices. In devices larger than the XC3020A and XC3120A FPGAs, two vertical Longlines in each column are connectable half-length lines. On the XC3020A and XC3120A FPGAs, only the outer Longlines are connectable half-length lines. Longlines can be driven by a logic block or IOB output on a column-by-column basis. This capability provides a common low skew control or clock line within each column of logic blocks. Interconnections of these Longlines are shown in Figure 15. Isolation buffers are provided at each input to a Longline and are enabled automatically by the development system when a connection is made.
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Figure 14: Horizontal and Vertical Longlines. These Longlines provide high fan-out, low-skew signal distribution in each row and column. The global buffer in the upper left die corner drives a common line throughout the FPGA.
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Figure 15: Programmable Interconnection of Longlines. This is provided at the edges of the routing area. Three-state buffers allow the use of horizontal Longlines to form on-chip wired AND and multiplexed buses. The left two non-clock vertical Longlines per column (except XC3020A) and the outer perimeter Longlines may be programmed as connectable half-length lines.
VCC Z = DA * DB * DC * ... * DN
VCC
(LOW) DA DB DC DN
X3036
Figure 16: 3-State Buffers Implement a Wired-AND Function. When all the buffer 3-state lines are High, (high impedance), the pull-up resistor(s) provide the High output. The buffer inputs are driven by the control signals or a Low.
Z = DA * A + DB * B + DC * C + ... + DN * N
DA WEAK KEEPER CIRCUIT A
DB B
DC C
DN N
X1741A
Figure 17: 3-State Buffers Implement a Multiplexer. The selection is accomplished by the buffer 3-state signal.
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A buffer in the upper left corner of the FPGA chip drives a global net which is available to all K inputs of logic blocks. Using the global buffer for a clock signal provides a skew-free, high fan-out, synchronized clock for use at any or all of the IOBs and CLBs. Configuration bits for the K input to each logic block can select this global line or another routing resource as the clock source for its flip-flops. This net may also be programmed to drive the die edge clock lines for IOB use. An enhanced speed, CMOS threshold, direct access to this buffer is available at the second pad from the top of the left die edge. A buffer in the lower right corner of the array drives a horizontal Longline that can drive programmed connections to a vertical Longline in each interconnection column. This alternate buffer also has low skew and high fan-out. The network formed by this alternate buffer's Longlines can be selected to drive the K inputs of the CLBs. CMOS threshold, high speed access to this buffer is available from the third pad from the bottom of the right die edge. of the 3-state buffer controls allows them to implement wide multiplexing functions. Any 3-state buffer input can be selected as drive for the horizontal long-line bus by applying a Low logic level on its 3-state control line. See Figure 16. The user is required to avoid contention which can result from multiple drivers with opposing logic levels. Control of the 3-state input by the same signal that drives the buffer input, creates an open-drain wired-AND function. A logic High on both buffer inputs creates a high impedance, which represents no contention. A logic Low enables the buffer to drive the Longline Low. See Figure 17. Pull-up resistors are available at each end of the Longline to provide a High output when all connected buffers are non-conducting. This forms fast, wide gating functions. When data drives the inputs, and separate signals drive the 3-state control lines, these buffers form multiplexers (3-state busses). In this case, care must be used to prevent contention through multiple active buffers of conflicting levels on a common line. Each horizontal Longline is also driven by a weak keeper circuit that prevents undefined floating levels by maintaining the previous logic level when the line is not driven by an active buffer or a pull-up resistor. Figure 18 shows 3-state buffers, Longlines and pull-up resistors.
Internal Busses
A pair of 3-state buffers, located adjacent to each CLB, permits logic to drive the horizontal Longlines. Logic operation
BIDIRECTIONAL INTERCONNECT BUFFERS
GLOBAL NET
3 VERTICAL LONG LINES PER COLUMN
7
I/O CLOCKS
GG
GH
P48
HORIZONTAL LONG LINE PULL-UP RESISTOR
HORIZONTAL LONG LINE
OSCILLATOR AMPLIFIER OUTPUT
P47
DIRECTINPUT OF P47 TO AUXILIARY BUFFER CRYSTAL OSCILLATOR BUFFER 3-STATE INPUT
HG
HH
BCL KIN
OS C
3-STATE CONTROL
.l .lk .q .ck .Q
P46
D P G M
3-STATE BUFFER
ALTERNATE BUFFER
P40 P41 P42 P43 RST
X1245
Figure 18: Design Editor. An extra large view of possible interconnections in the lower right corner of the XC3020A.
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Crystal Oscillator
Figure 18 also shows the location of an internal high speed inverting amplifier that may be used to implement an on-chip crystal oscillator. It is associated with the auxiliary buffer in the lower right corner of the die. When the oscillator is configured and connected as a signal source, two special user IOBs are also configured to connect the oscillator amplifier with external crystal oscillator components as shown in Figure 19. A divide by two option is available to assure symmetry. The oscillator circuit becomes active early in the configuration process to allow the oscillator to stabilize. Actual internal connection is delayed until completion of configuration. In Figure 19 the feedback resistor R1, between the output and input, biases the amplifier at threshold. The inversion of the amplifier, together with the R-C networks and an AT-cut series resonant crystal, produce the 360-degree phase shift of the Pierce oscillator. A
series resistor R2 may be included to add to the amplifier output impedance when needed for phase-shift control, crystal resistance matching, or to limit the amplifier input swing to control clipping at large amplitudes. Excess feedback voltage may be corrected by the ratio of C2/C1. The amplifier is designed to be used from 1 MHz to about one-half the specified CLB toggle frequency. Use at frequencies below 1 MHz may require individual characterization with respect to a series resistance. Crystal oscillators above 20 MHz generally require a crystal which operates in a third overtone mode, where the fundamental frequency must be suppressed by an inductor across C2, turning this parallel resonant circuit to double the fundamental crystal frequency, i.e., 2/3 of the desired third harmonic frequency network. When the oscillator inverter is not used, these IOBs and their package pins are available for general user I/O.
D
Q Internal External
Alternate Clock Buffer
XTAL1
XTAL2 (IN) R1 Suggested Component Values R1 0.5 - 1 M R2 0 - 1 k (may be required for low frequency, phase shift and/or compensation level for crystal Q) C1, C2 10 - 40 pF Y1 1 - 20 MHz AT-cut parallel resonant 44 PIN PLCC 30 26 68 PIN PLCC 47 43 84 PIN PGA PLCC J11 57 L11 53 100 PIN CQFP PQFP 82 67 76 61 R2 Y1 C1 C2
XTAL 1 (OUT) XTAL 2 (IN)
132 PIN PGA P13 M13
160 PIN PQFP 82 76
164 PIN CQFP 105 99
175 PIN 176 PIN 208 PIN TQFP PQFP PGA 91 110 T14 85 100 P15
X7064
Figure 19: Crystal Oscillator Inverter. When activated, and by selecting an output network for its buffer, the crystal oscillator inverter uses two unconfigured package pins and external components to implement an oscillator. An optional divide-by-two mode is available to assure symmetry.
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Configuration
Initialization Phase
An internal power-on-reset circuit is triggered when power is applied. When VCC reaches the voltage at which portions of the FPGA device begin to operate (nominally 2.5 to 3 V), the programmable I/O output buffers are 3-stated and a high-impedance pull-up resistor is provided for the user I/O pins. A time-out delay is initiated to allow the power supply voltage to stabilize. During this time the power-down mode is inhibited. The Initialization state time-out (about 11 to 33 ms) is determined by a 14-bit counter driven by a self-generated internal timer. This nominal 1-MHz timer is subject to variations with process, temperature and power supply. As shown in Table 1, five configuration mode choices are available as determined by the input levels of three mode pins; M0, M1 and M2. Table 1: Configuration Mode Choices
M0 M1 M2 CCLK 0 0 0 output 0 0 1 output 0 1 0-- 0 1 1 output 1 0 0-- 1 0 1 output 1 1 0-- 1 1 1 input Mode Master Master reserved Master reserved Peripheral reserved Slave Data Bit Serial Byte Wide Addr. = 0000 up -- Byte Wide Addr. = FFFF down -- Byte Wide -- Bit Serial
In Master configuration modes, the device becomes the source of the Configuration Clock (CCLK). The beginning of configuration of devices using Peripheral or Slave modes must be delayed long enough for their initialization to be completed. An FPGA with mode lines selecting a Master configuration mode extends its initialization state using four times the delay (43 to 130 ms) to assure that all daisy-chained slave devices, which it may be driving, will be ready even if the master is very fast, and the slave(s) very slow. Figure 20 shows the state sequences. At the end of Initialization, the device enters the Clear state where it clears the configuration memory. The active Low, open-drain initialization signal INIT indicates when the Initialization and Clear states are complete. The FPGA tests for the absence of an external active Low RESET before it makes a final sample of the mode lines and enters the Configuration state. An external wired-AND of one or more INIT pins can be used to control configuration by the assertion of the active-Low RESET of a master mode device or to signal a processor that the FPGAs are not yet initialized. If a configuration has begun, a re-assertion of RESET for a minimum of three internal timer cycles will be recognized and the FPGA will initiate an abort, returning to the Clear state to clear the partially loaded configuration memory words. The FPGA will then resample RESET and the mode lines before re-entering the Configuration state. During configuration, the XC3000A, XC3000L, XC3100A, and XC3100L devices check the bit-stream format for stop bits in the appropriate positions. Any error terminates the configuration and pulls INIT Low.
7
All User I/O Pins 3-Stated with High Impedance Pull-Up, HDC=High, LDC=Low
INIT Output = Low PWRDWN Inactive
Power Down No HDC, LDC or Pull-Up
Initialization Power-On Time Delay Active RESET
PWRDWN Active
Clear Configuration Memory
RESET Active
No
Test Mode Pins
Configuration Program Mode
Start-Up
Operational Mode
Low on DONE/PROGRAM and RESET
Active RESET Operates on User Logic Clear Is ~ 200 Cycles for the XC3020A--130 to 400 s ~ 250 Cycles for the XC3030A--165 to 500 s ~ 290 Cycles for the XC3042A--195 to 580 s ~ 330 Cycles for the XC3064A--220 to 660 s ~ 375 Cycles for the XC3090A--250 to 750 s
Power-On Delay is 214 Cycles for Non-Master Mode--11 to 33 ms 216 Cycles for Master Mode--43 to 130 ms
X3399
Figure 20: A State Diagram of the Configuration Process for Power-up and Reprogram.
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A re-program is initiated.when a configured XC3000 series device senses a High-to-Low transition and subsequent >6 s Low level on the DONE/PROG package pin, or, if this pin is externally held permanently Low, a High-to-Low transition and subsequent >6 s Low time on the RESET package pin. The device returns to the Clear state where the configuration memory is cleared and mode lines re-sampled, as for an aborted configuration. The complete configuration program is cleared and loaded during each configuration program cycle. Length count control allows a system of multiple Field Programmable Gate Arrays, of assorted sizes, to begin operation in a synchronized fashion. The configuration program
11111111 0010 < 24-Bit Length Count > 1111 0 111 0 111 0 111 . . . . . . . . . 0 111 0 111 1111
generated by the development system begins with a preamble of 111111110010 followed by a 24-bit length count representing the total number of configuration clocks needed to complete loading of the configuration program(s). The data framing is shown in Figure 21. All FPGAs connected in series read and shift preamble and length count in on positive and out on negative configuration clock edges. A device which has received the preamble and length count then presents a High Data Out until it has intercepted the appropriate number of data frames. When the configuration program memory of an FPGA is full and the length count does not yet compare, the device shifts any additional data through, as it did for preamble and length count. When the FPGA configuration memory is full and the length count compares, the device will execute
--Dummy Bits* --Preamble Code --Configuration Program Length --Dummy Bits (4 Bits Minimum)
Header
For XC3120 197 Configuration Data Frames (Each Frame Consists of: A Start Bit (0) A 71-Bit Data Field Three Stop Bits Postamble Code (4 Bits Minimum)
X5300_01
Program Data Repeated for Each Logic Cell Array in a Daisy Chain
*The LCA Device Require Four Dummy Bits Min; Software Generates Eight Dummy Bits
Device Gates CLBs Row x Col IOBs Flip-flops Horizontal Longlines TBUFs/Horizontal LL Bits per Frame (including1 start and 3 stop bits) Frames Program Data = Bits x Frames + 4 bits (excludes header) PROM size (bits) = Program Data + 40-bit Header
XC3020A XC3020L XC3120A 1,000 to 1,500 64 (8 x 8) 64 256 16 9 75 197 14,779
XC3030A XC3030L XC3130A 1,500 to 2,000 100 (10 x 10) 80 360 20 11 92 241 22,176
XC3042A XC3042L XC3142A XC3142L 2,000 to 3,000 144 (12 x 12) 96 480 24 13 108 285 30,784
XC3064A XC3064L XC3164A 3,500 to 4,500 224 (16 x 14) 120 688 32 15 140 329 46,064
XC3090A XC3090L XC3190A XC3190L 5,000 to 6,000 320 (20 x 16) 144 928 40 17 172 373 64,160
XC3195A 6,500 to 7,500 484 (22 x 22) 176 1,320 44 23 188 505 94,944
14,819
22,216
30,824
46,104
64,200
94,984
Figure 21: Internal Configuration Data Structure for an FPGA. This shows the preamble, length count and data frames generated by the Development System. The Length Count produced by the program = [(40-bit preamble + sum of program data + 1 per daisy chain device) rounded up to multiple of 8] - (2 K 4) where K is a function of DONE and RESET timing selected. An additional 8 is added if roundup increment is less than K. K additional clocks are needed to complete start-up after length count is reached.
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a synchronous start-up sequence and become operational. See Figure 22. Two CCLK cycles after the completion of loading configuration data, the user I/O pins are enabled as configured. As selected, the internal user-logic RESET is released either one clock cycle before or after the I/O pins become active. A similar timing selection is programmable for the DONE/PROG output signal. DONE/PROG may also be programmed to be an open drain or include a pull-up resistor to accommodate wired ANDing. The High During Configuration (HDC) and Low During Configuration (LDC) are two user I/O pins which are driven active while an FPGA is in its Initialization, Clear or Configure states. They and DONE/PROG provide signals for control of external logic signals such as RESET, bus enable or PROM enable during configuration. For parallel Master configuration modes, these signals provide PROM enable control and allow the data pins to be shared with user logic signals. User I/O inputs can be programmed to be either TTL or CMOS compatible thresholds. At power-up, all inputs have TTL thresholds and can change to CMOS thresholds at the completion of configuration if the user has selected CMOS thresholds. The threshold of PWRDWN and the direct clock inputs are fixed at a CMOS level. If the crystal oscillator is used, it will begin operation before configuration is complete to allow time for stabilization before it is connected to the internal circuitry.
Configuration Data
Configuration data to define the function and interconnection within a Field Programmable Gate Array is loaded from an external storage at power-up and after a re-program signal. Several methods of automatic and controlled loading of the required data are available. Logic levels applied to mode selection pins at the start of configuration time determine the method to be used. See Table 1. The data may be either bit-serial or byte-parallel, depending on the configuration mode. The different FPGAs have different sizes and numbers of data frames. To maintain compatibility between various device types, the Xilinx product families use compatible configuration formats. For the XC3020A, configuration requires 14779 bits for each device, arranged in 197 data frames. An additional 40 bits are used in the header. See Figure 22. The specific data format for each device is produced by the development system and one or more of these files can then be combined and appended to a length count preamble and be transformed into a PROM format file by the development system. A compatibility exception precludes the use of an XC2000-series device as the master for XC3000-series devices if their DONE or RESET are programmed to occur after their outputs become active. The Tie Option defines output levels of unused blocks of a design and connects these to unused routing resources. This prevents indeterminate levels that might produce parasitic supply currents. If unused blocks are not sufficient to complete the tie, the user can indicate nets which must not
Postamble Last Frame
7
Data Frame 12 24 4 3
3 STOP
4
DIN
Stop
Preamble
Length Count
Data
Start Bit Start Bit The configuration data consists of a composite * 40-bit preamble/length count, followed by one or more concatenated FPGA programs, separated by 4-bit postambles. An additional final postamble bit is added for each slave device and the result rounded up to a byte boundary. The length count is two less than the number of resulting bits. Timing of the assertion of DONE and termination of the INTERNAL RESET may each be programmed to occur one cycle before or after the I/O outputs become active. Heavy lines indicate the default condition
Length Count*
Weak Pull-Up
I/O Active
PROGRAM
DONE
Internal Reset
X5988
Figure 22: Configuration and Start-up of One or More FPGAs.
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be used to drive the remaining unused routing, as that might affect timing of user nets. Tie can be omitted for quick breadboard iterations where a few additional milliamps of Icc are acceptable. The configuration bitstream begins with eight High preamble bits, a 4-bit preamble code and a 24-bit length count. When configuration is initiated, a counter in the FPGA is set to zero and begins to count the total number of configuration clock cycles applied to the device. As each configuration data frame is supplied to the device, it is internally assembled into a data word, which is then loaded in parallel into one word of the internal configuration memory array. The configuration loading process is complete when the current length count equals the loaded length count and the required configuration program data frames have been written. Internal user flip-flops are held Reset during configuration. Two user-programmable pins are defined in the unconfigured Field Programmable Gate Array. High During Configuration (HDC) and Low During Configuration (LDC) as well as DONE/PROG may be used as external control signals during configuration. In Master mode configurations it is convenient to use LDC as an active-Low EPROM Chip Enable. After the last configuration data bit is loaded and the length count compares, the user I/O pins become active. Options allow timing choices of one clock earlier or later for the timing of the end of the internal logic RESET and the assertion of the DONE signal. The open-drain DONE/PROG output can be AND-tied with multiple devices and used as an active-High READY, an active-Low PROM enable or a RESET to other portions of the system. The state diagram of Figure 20 illustrates the configuration process.
Peripheral Mode
Peripheral mode provides a simplified interface through which the device may be loaded byte-wide, as a processor peripheral. Figure 27 shows the peripheral mode connections. Processor write cycles are decoded from the common assertion of the active low Write Strobe (WS), and two active low and one active high Chip Selects (CS0, CS1, CS2). The FPGA generates a configuration clock from the internal timing generator and serializes the parallel input data for internal framing or for succeeding slaves on Data Out (DOUT). A output High on READY/BUSY pin indicates the completion of loading for each byte when the input register is ready for a new byte. As with Master modes, Peripheral mode may also be used as a lead device for a daisy-chain of slave devices.
Slave Serial Mode
Slave Serial mode provides a simple interface for loading the Field Programmable Gate Array configuration as shown in Figure 29. Serial data is supplied in conjunction with a synchronizing input clock. Most Slave mode applications are in daisy-chain configurations in which the data input is driven from the previous FPGA's data out, while the clock is supplied by a lead device in Master or Peripheral mode. Data may also be supplied by a processor or other special circuits.
Daisy Chain
The development system is used to create a composite configuration for selected FPGAs including: a preamble, a length count for the total bitstream, multiple concatenated data programs and a postamble plus an additional fill bit per device in the serial chain. After loading and passing-on the preamble and length count to a possible daisy-chain, a lead device will load its configuration data frames while providing a High DOUT to possible down-stream devices as shown in Figure 25. Loading continues while the lead device has received its configuration program and the current length count has not reached the full value. The additional data is passed through the lead device and appears on the Data Out (DOUT) pin in serial form. The lead device also generates the Configuration Clock (CCLK) to synchronize the serial output data and data in of down-stream FPGAs. Data is read in on DIN of slave devices by the positive edge of CCLK and shifted out the DOUT on the negative edge of CCLK. A parallel Master mode device uses its internal timing generator to produce an internal CCLK of 8 times its EPROM address rate, while a Peripheral mode device produces a burst of 8 CCLKs for each chip select and write-strobe cycle. The internal timing generator continues to operate for general timing and synchronization of inputs in all modes.
Configuration Modes
Master Mode
In Master mode, the FPGA automatically loads configuration data from an external memory device. There are three Master modes that use the internal timing source to supply the configuration clock (CCLK) to time the incoming data. Master Serial mode uses serial configuration data supplied to Data-in (DIN) from a synchronous serial source such as the Xilinx Serial Configuration PROM shown in Figure 23. Master Parallel Low and High modes automatically use parallel data supplied to the D0-D7 pins in response to the 16-bit address generated by the FPGA. Figure 25 shows an example of the parallel Master mode connections required. The HEX starting address is 0000 and increments for Master Low mode and it is FFFF and decrements for Master High mode. These two modes provide address compatibility with microprocessors which begin execution from opposite ends of memory.
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XC3000 Series Field Programmable Gate Arrays Special Configuration Functions
The configuration data includes control over several special functions in addition to the normal user logic functions and interconnect. * * * * * * Input thresholds Readback disable DONE pull-up resistor DONE timing RESET timing Oscillator frequency divided by two configuration, each Readback frame has only one Stop bit (read back as a zero). The third leading dummy bit mentioned above can be considered the Start bit of the first frame. All data frames must be read back to complete the process and return the Mode Select and CCLK pins to their normal functions. Readback data includes the current state of each CLB flip-flop, each input flip-flop or latch, and each device pad. These data are imbedded into unused configuration bit positions during Readback. This state information is used by the development system In-Circuit Verifier to provide visibility into the internal operation of the logic while the system is operating. To readback a uniform time-sample of all storage elements, it may be necessary to inhibit the system clock.
Each of these functions is controlled by configuration data bits which are selected as part of the normal development system bitstream generation process.
Input Thresholds
Prior to the completion of configuration all FPGA input thresholds are TTL compatible. Upon completion of configuration, the input thresholds become either TTL or CMOS compatible as programmed. The use of the TTL threshold option requires some additional supply current for threshold shifting. The exception is the threshold of the PWRDWN input and direct clocks which always have a CMOS input. Prior to the completion of configuration the user I/O pins each have a high impedance pull-up. The configuration program can be used to enable the IOB pull-up resistors in the Operational mode to act either as an input load or to avoid a floating input on an otherwise unused pin.
Reprogram
To initiate a re-programming cycle, the dual-function pin DONE/PROG must be given a High-to-Low transition. To reduce sensitivity to noise, the input signal is filtered for two cycles of the FPGA internal timing generator. When reprogram begins, the user-programmable I/O output buffers are disabled and high-impedance pull-ups are provided for the package pins. The device returns to the Clear state and clears the configuration memory before it indicates `initialized'. Since this Clear operation uses chip-individual internal timing, the master might complete the Clear operation and then start configuration before the slave has completed the Clear operation. To avoid this problem, the slave INIT pins must be AND-wired and used to force a RESET on the master (see Figure 25). Reprogram control is often implemented using an external open-collector driver which pulls DONE/PROG Low. Once a stable request is recognized, the DONE/PROG pin is held Low until the new configuration has been completed. Even if the re-program request is externally held Low beyond the configuration period, the FPGA will begin operation upon completion of configuration.
7
Readback
The contents of a Field Programmable Gate Array may be read back if it has been programmed with a bitstream in which the Readback option has been enabled. Readback may be used for verification of configuration and as a method of determining the state of internal logic nodes during debugging. There are three options in generating the configuration bitstream. * * * "Never" inhibits the Readback capability. "One-time," inhibits Readback after one Readback has been executed to verify the configuration. "On-command" allows unrestricted use of Readback.
DONE Pull-up
DONE/PROG is an open-drain I/O pin that indicates the FPGA is in the operational state. An optional internal pull-up resistor can be enabled by the user of the development system. The DONE/PROG pins of multiple FPGAs in a daisy-chain may be connected together to indicate all are DONE or to direct them all to reprogram.
Readback is accomplished without the use of any of the user I/O pins; only M0, M1 and CCLK are used. The initiation of Readback is produced by a Low to High transition of the M0/RTRIG (Read Trigger) pin. The CCLK input must then be driven by external logic to read back the configuration data. The first three Low-to-High CCLK transitions clock out dummy data. The subsequent Low-to-High CCLK transitions shift the data frame information out on the M1/RDATA (Read Data) pin. Note that the logic polarity is always inverted, a zero in configuration becomes a one in Readback, and vice versa. Note also that each Readback frame has one Start bit (read back as a one) but, unlike in
DONE Timing
The timing of the DONE status signal can be controlled by a selection to occur either a CCLK cycle before, or after, the outputs going active. See Figure 22. This facilitates control of external functions such as a PROM enable or holding a system in a wait state.
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RESET Timing
As with DONE timing, the timing of the release of the internal reset can be controlled to occur either a CCLK cycle before, or after, the outputs going active. See Figure 22. This reset keeps all user programmable flip-flops and latches in a zero state during configuration. but with incorrect configuration and the possibility of internal contention. An XC3000A/XC3100A/XC3000L/XC3100L device starts any new frame only if the three preceding bits are all ones. If this check fails, it pulls INIT Low and stops the internal configuration, although the Master CCLK keeps running. The user must then start a new configuration by applying a >6 s Low level on RESET. This simple check does not protect against random bit errors, but it offers almost 100 percent protection against erroneous configuration files, defective configuration data sources, synchronization errors between configuration source and FPGA, or PC-board level defects, such as broken lines or solder-bridges.
Crystal Oscillator Division
A selection allows the user to incorporate a dedicated divide-by-two flip-flop between the crystal oscillator and the alternate clock line. This guarantees a symmetrical clock signal. Although the frequency stability of a crystal oscillator is very good, the symmetry of its waveform can be affected by bias or feedback drive.
Bitstream Error Checking
Bitstream error checking protects against erroneous configuration. Each Xilinx FPGA bitstream consists of a 40-bit preamble, followed by a device-specific number of data frames. The number of bits per frame is also device-specific; however, each frame ends with three stop bits (111) followed by a start bit for the next frame (0). All devices in all XC3000 families start reading in a new frame when they find the first 0 after the end of the previous frame. An original XC3000 device does not check for the correct stop bits, but XC3000A, XC3100A, XC3000L, and XC3100L devices check that the last three bits of any frame are actually 111. Under normal circumstances, all these FPGAs behave the same way; however, if the bitstream is corrupted, an XC3000 device will always start a new frame as soon as it finds the first 0 after the end of the previous frame, even if the data is completely wrong or out-of-sync. Given sufficient zeros in the data stream, the device will also go Done,
Reset Spike Protection
A separate modification slows down the RESET input before configuration by using a two-stage shift register driven from the internal clock. It tolerates submicrosecond High spikes on RESET before configuration. The XC3000 master can be connected like an XC4000 master, but with its RESET input used instead of INIT. (On XC3000, INIT is output only).
Soft Start-up
After configuration, the outputs of all FPGAs in a daisy-chain become active simultaneously, as a result of the same CCLK edge. In the original XC3000/3100 devices, each output becomes active in either fast or slew-rate limited mode, depending on the way it is configured. This can lead to large ground-bounce signals. In XC3000A, XC3000L, XC3100A, and XC3100L devices, all outputs become active first in slew-rate limited mode, reducing the ground bounce. After this soft start-up, each individual output slew rate is again controlled by the respective configuration bit.
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Configuration Timing
This section describes the configuration modes in detail.
Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA drives a Xilinx Serial PROM that feeds the DIN input. Each rising edge of the CCLK output increments the Serial PROM internal address counter. This puts the next data bit on the SPROM data output, connected to the DIN pin. The lead FPGA accepts this data on the subsequent rising CCLK edge. The lead FPGA then presents the preamble data (and all data that overflows the lead device) on its DOUT pin. There is an internal delay of 1.5 CCLK periods, which means that
* IF READBACK IS ACTIVATED, A 5-k RESISTOR IS REQUIRED IN SERIES WITH M1 DURING CONFIGURATION THE 5 k M2 PULL-DOWN RESISTOR OVERCOMES THE INTERNAL PULL-UP, BUT IT ALLOWS M2 TO BE USER I/O. * +5 V
DOUT changes on the falling CCLK edge, and the next device in the daisy-chain accepts data on the subsequent rising CCLK edge. The SPROM CE input can be driven from either LDC or DONE. Using LDC avoids potential contention on the DIN pin, if this pin is configured as user-I/O, but LDC is then restricted to be a permanently High user output. Using DONE also avoids contention on DIN, provided the early DONE option is invoked.
M0
M1
PWRDWN TO DIN OF OPTIONAL DAISY-CHAINED LCAs WITH DIFFERENT CONFIGURATIONS TO CCLK OF OPTIONAL DAISY-CHAINED LCAs WITH DIFFERENT CONFIGURATIONS
DOUT M2
+5V
HDC LDC GENERALPURPOSE USER I/O PINS INIT
7
OTHER I/O PINS TO CCLK OF OPTIONAL SLAVE LCAs WITH IDENTICAL CONFIGURATIONS TO DIN OF OPTIONAL SLAVE LCAs WITH IDENTICAL CONFIGURATIONS
RESET
Figure 23: Master Serial Mode Circuit Diagram
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* * * * *
XC3000 FPGA DEVICE
+5 V
RESET VCC DIN CCLK D/P
INIT
VPP DATA SCP CEO CLK CE CASCADED SERIAL MEMORY
DATA CLK CE OE/RESET XC17xx
OE/RESET
(LOW RESETS THE XC17xx ADDRESS POINTER)
X5989_01
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CCLK (Output) 2 TCKDS 1 Serial Data In TDSCK n n+1 n+2
Serial DOUT (Output)
n-3
n-2
n-1
n
X3223
CCLK
Description Data In setup Data In hold
Symbol 1 2 TDSCK CKDS
Min 60 0
Max
Units ns ns
Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a non-monotonically rising VCC may require >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P after VCC has reached 4.0 V (2.5 V for the XC3000L). 2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is High. 3. Master-serial-mode timing is based on slave-mode testing.
Figure 24: Master Serial Mode Programming Switching Characteristics
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XC3000 Series Field Programmable Gate Arrays Master Parallel Mode
In Master Parallel mode, the lead FPGA directly addresses an industry-standard byte-wide EPROM and accepts eight data bits right before incrementing (or decrementing) the address outputs. The eight data bits are serialized in the lead FPGA, which then presents the preamble data (and all data that overflows the lead device) on the DOUT pin. There is an internal delay of 1.5 CCLK periods, after the rising CCLK edge that accepts a byte of data, and also changes the EPROM address, until the falling CCLK edge that makes the LSB (D0) of this byte appear at DOUT. This means that DOUT changes on the falling CCLK edge, and the next device in the daisy chain accepts data on the subsequent rising CCLK edge.
* If Readback is
+5 V
*
+5 V
+5 V
*
M0 M1PWRDWN CCLK DIN DOUT FPGA Slave #1 5 k
+5 V
*
M0 M1PWRDWN CCLK DIN DOUT FPGA Slave #n 5 k
Activated, a 5-k Resistor is Required in Series With M1 5 k
M0 M1PWRDWN CCLK DOUT M2 HDC RCLK
...
M2 HDC LDC GeneralPurpose User I/O Pins
M2 HDC LDC GeneralPurpose User I/O Pins
GeneralPurpose User I/O Pins
A15 A14 A13
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 OE N.C. CE 8 D7 D6 D5 D4 D3 D2 D1 D0 D/P RESET EPROM
Other I/O Pins FPGA Master D7 D6 D5 D4 D3 D2 D1 D0
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D/P
Other I/O Pins INIT
Other I/O Pins INIT D/P Reset
...
...
.....
Reprogram System Reset
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Note: XC2000 Devices Do Not Have INIT to Hold Off a Master Device. Reset of a Master Device Should be Asserted by an External Timing Circuit to Allow for LCA CCLK Variations in Clear State Time.
RESET
INIT
+5 V Open Collector 5 k Each
X5990
Figure 25: Master Parallel Mode Circuit Diagram
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XC3000 Series Field Programmable Gate Arrays
A0-A15 (output)
Address for Byte n
Address for Byte n + 1 1 TRAC
D0-D7
Byte 2 TDRC 3 TRCD
RCLK (output) 7 CCLKs CCLK
CCLK (output)
DOUT (output)
D6 Byte n - 1
D7
X5380
RCLK
Description To address valid To data setup To data hold RCLK High RCLK Low
1 2 3
Symbol TRAC TDRC TRCD TRCH TRCL
Min 0 60 0 600 4.0
Max 200
Units ns ns ns ns s
Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a non-monotonically rising VCC may require a >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P after VCC has reached 4.0 V (2.5 V for the XC3000L). 2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is High.
This timing diagram shows that the EPROM requirements are extremely relaxed: EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements.
Figure 26: Master Parallel Mode Programming Switching Characteristics
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XC3000 Series Field Programmable Gate Arrays Peripheral Mode
Peripheral mode uses the trailing edge of the logic AND condition of the CS0, CS1, CS2, and WS inputs to accept byte-wide data from a microprocessor bus. In the lead FPGA, this data is loaded into a double-buffered UART-like parallel-to-serial converter and is serially shifted into the internal logic. The lead FPGA presents the preamble data (and all data that overflows the lead device) on the DOUT pin. The Ready/Busy output from the lead device acts as a handshake signal to the microprocessor. RDY/BUSY goes Low when a byte has been received, and goes High again
CONTROL SIGNALS ADDRESS BUS DATA BUS 8 M0 D0-7
when the byte-wide input buffer has transferred its information into the shift register, and the buffer is ready to receive new data. The length of the BUSY signal depends on the activity in the UART. If the shift register had been empty when the new byte was received, the BUSY signal lasts for only two CCLK periods. If the shift register was still full when the new byte was received, the BUSY signal can be as long as nine CCLK periods. Note that after the last byte has been entered, only seven of its bits are shifted out. CCLK remains High with DOUT equal to bit 6 (the next-to-last bit) of the last byte entered.
+5 V * 5 k * IF READBACK IS ACTIVATED, A 5-k RESISTOR IS REQUIRED IN SERIES WITH M1
M1 PWR DWN CCLK
D0-7
DOUT ADDRESS DECODE LOGIC CS0 M2 HDC FPGA CS1 CS2 OTHER I/O PINS RDY/BUSY WS INIT REPROGRAM OC D/P RESET LDC
OPTIONAL DAISY-CHAINED FPGAs WITH DIFFERENT CONFIGURATIONS
...
+5 V
GENERALPURPOSE USER I/O PINS
7
...
X5991
Figure 27: Peripheral Mode Circuit Diagram
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XC3000 Series Field Programmable Gate Arrays
WRITE TO FPGA WS, CS0, CS1
CS2 TCA
1
2 TDC D0-D7 Valid
TCD
3
CCLK 4 TWTRB RDY/BUSY TBUSY 6
DOUT
D6
D7 Previous Byte
D0
D1
D2 New Byte
X5992
WRITE
Description Effective Write time required (Assertion of CS0, CS1, CS2, WS) DIN Setup time required DIN Hold time required RDY/BUSY delay after end of WS Earliest next WS after end of BUSY
1 2 3 4 5 6
Symbol TCA TDC TCD TWTRB TRBWT TBUSY
Min 100 60 0
Max
Units ns ns ns ns ns
60 0 2.5 9
RDY
BUSY Low time generated
CCLK periods
Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a non-monotonically rising VCC may require a >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P after VCC has reached 4.0 V (2.5 V for the XC3000L). 2. Configuration must be delayed until the INIT of all FPGAs is High. 3. Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and the phase of the internal timing generator for CCLK. 4. CCLK and DOUT timing is tested in slave mode. 5. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest TBUSY occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is loaded into the input register before the second-level buffer has started shifting out data.
Note: This timing diagram shows very relaxed requirements: Data need not be held beyond the rising edge of WS. BUSY will go active within 60 ns after the end of WS. BUSY will stay active for several microseconds. WS may be asserted immediately after the end of BUSY. Figure 28: Peripheral Mode Programming Switching Characteristics
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XC3000 Series Field Programmable Gate Arrays Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK input(s) of the FPGA(s). The serial configuration bitstream must be available at the DIN input of the lead FPGA a short set-up time before each rising CCLK edge. The lead device then presents the preamble data (and all data that overflows the lead device) on its DOUT pin. There is an internal delay of 0.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next device in the daisy-chain accepts data on the subsequent rising CCLK edge.
* If Readback is Activated, a 5-k Resistor is Required in Series with M1 5 k Optional Daisy-Chained LCAs with Different Configurations
+5 V
*
M0 Micro Computer STRB D0 D1 I/O Port D2 D3 D4 D5 D6 D7 RESET INIT RESET +5 V CCLK DIN
M1
PWRDWN
M2 DOUT HDC LDC GeneralPurpose User I/O Pins
FPGA
Other I/O Pins D/P
...
7
X5993
Figure 29: Slave Serial Mode Circuit Diagram
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XC3000 Series Field Programmable Gate Arrays
DIN 1 TDCC CCLK
Bit n 2 TCCD
Bit n + 1 5 TCCL
4 TCCH DOUT (Output) Bit n - 1
3 TCCO Bit n
X5379
Description To DOUT DIN setup DIN hold High time Low time (Note 1) Frequency
3 1 2 4 5
Symbol TCCO TDCC TCCD TCCH TCCL FCC
Min
Max 100
Units ns ns ns s s MHz
CCLK
60 0 0.05 0.05
5.0 10
Notes: 1. The max limit of CCLK Low time is caused by dynamic circuitry inside the FPGA. 2. Configuration must be delayed until the INIT of all FPGAs is High. 3. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a non-monotonically rising VCC may require a >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P after VCC has reached 4.0 V (2.5 V for the XC3000L).
Figure 30: Slave Serial Mode Programming Switching Characteristics
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XC3000 Series Field Programmable Gate Arrays Program Readback Switching Characteristics
DONE/PROG (OUTPUT) 1 TRTH RTRIG (M0) 2 TRTCC 4 TCCL 4 TCCL
CCLK(1) 5 3 TCCRD M1 Input/ RDATA Output HI-Z VALID READBACK OUTPUT VALID READBACK OUTPUT
X6116
RTRIG CCLK
Description RTRIG High RTRIG setup RDATA delay High time Low time
1 2 3 4 5
Symbol TRTH TRTCC TCCRD TCCHR TCCLR
Min 250 200 0.5 0.5
Max
100 5
Units ns ns ns s s
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Notes: 1. 2. 3. 4.
During Readback, CCLK frequency may not exceed 1 MHz. RETRIG (M0 positive transition) shall not be done until after one clock following active I/O pins. Readback should not be initiated until configuration is complete. TCCLR is 5 s min to 15 s max for XC3000L.
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XC3000 Series Field Programmable Gate Arrays
General XC3000 Series Switching Characteristics
4 TMRW RESET 2 TMR 3 TRM M0/M1/M2 5 TPGW DONE/PROG 6 TPGI INIT (Output) User State Clear State Configuration State
PWRDWN Note 3 VCC (Valid) VCCPD
X5387
Description M0, M1, M2 setup time required M0, M1, M2 hold time required RESET (2) RESET Width (Low) req. for Abort Width (Low) required for Re-config. DONE/PROG INIT response after D/P is pulled Low PWRDWN (3) Power Down VCC
2 3 4 5 6
Symbol TMR TRM TMRW TPGW TPGI VCCPD
Min 1 4.5 6 6 2.3
Max
7
Units s s s s s V
Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vcc has reached 4.0 V (2.5 V for XC3000L). A very long Vcc rise time of >100 ms, or a non-monotonically rising VCC may require a >1-s High level on RESET, followed by a >6-s Low level on RESET and D/P after Vcc has reached 4.0 V (2.5 V for XC3000L). 2. RESET timing relative to valid mode lines (M0, M1, M2) is relevant when RESET is used to delay configuration. The specified hold time is caused by a shift-register filter slowing down the response to RESET during configuration. 3. PWRDWN transitions must occur while VCC >4.0 V(2.5 V for XC3000L).
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XC3000 Series Field Programmable Gate Arrays
Device Performance
The XC3000 families of FPGAs can achieve very high performance. This is the result of * A sub-micron manufacturing process, developed and continuously being enhanced for the production of state-of-the-art CMOS SRAMs. Careful optimization of transistor geometries, circuit design, and lay-out, based on years of experience with the XC3000 family. A look-up table based, coarse-grained architecture that can collapse multiple-layer combinatorial logic into a single function generator. One CLB can implement up to four layers of conventional logic in as little as 1.5 ns.
duced by storage elements. Loading of a logic-block output is limited only by the resulting propagation delay of the larger interconnect network. Speed performance of the logic block is a function of supply voltage and temperature. See Figure 32. Interconnect performance depends on the routing resources used to implement the signal path. Direct interconnects to the neighboring CLB provide an extremely fast path. Local interconnects go through switch matrices (magic boxes) and suffer an RC delay, equal to the resistance of the pass transistor multiplied by the capacitance of the driven metal line. Longlines carry the signal across the length or breadth of the chip with only one access delay. Generous on-chip signal buffering makes performance relatively insensitive to signal fan-out; increasing fan-out from 1 to 8 changes the CLB delay by only 10%. Clocks can be distributed with two low-skew clock distribution networks. The tools in the Development System used to place and route a design in an XC3000 FPGA automatically calculate the actual maximum worst-case delays along each signal path. This timing information can be back-annotated to the design's netlist for use in timing simulation or examined with, a static timing analyzer. Actual system performance is applications dependent. The maximum clock rate that can be used in a system is determined by the critical path delays within that system. These delays are combinations of incremental logic and routing delays, and vary from design to design. In a synchronous system, the maximum clock rate depends on the number of combinatorial logic layers between re-synchronizing flip-flops. Figure 33 shows the achievable clock rate as a function of the number of CLB layers.
*
*
Actual system performance is determined by the timing of critical paths, including the delay through the combinatorial and sequential logic elements within CLBs and IOBs, plus the delay in the interconnect routing. The AC-timing specifications state the worst-case timing parameters for the various logic resources available in the XC3000-families architecture. Figure 31 shows a variety of elements involved in determining system performance. Logic block performance is expressed as the propagation time from the interconnect point at the input to the block to the output of the block in the interconnect area. Since combinatorial logic is implemented with a memory lookup table within a CLB, the combinatorial delay through the CLB, called TILO, is always the same, regardless of the function being implemented. For the combinatorial logic function driving the data input of the storage element, the critical timing is data set-up relative to the clock edge provided to the flip-flop element. The delay from the clock source to the output of the logic block is critical in the timing signals pro-
7
Clock to Output TCKO CLB
Combinatorial TILO CLB Logic Logic
Setup TICK CLB IOB TOP
PAD
(K) CLOCK IOB PAD T PID
(K)
TCKO
TOKPO
X3178
Figure 31: Primary Block Speed Factors. Actual timing is a function of various block factors combined with routing. factors. Overall performance can be evaluated with the timing calculator or by an optional simulation.
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XC3000 Series Field Programmable Gate Arrays
SPECIFIED WORST-CASE VALUES
1.00
V) 4.75 AL ( RCI ME COM MAX
MAX
TA MILI
RY (
4.5 V
)
0.80 NORMALIZED DELAY
0.60
TYPICAL COMMERCIAL (+ 5.0 V, 25C)
TYPICAL MILITARY 0.40
.75 V) ERCIAL (4 MIN COMM L (5.25 V) MMERCIA MIN CO
MIN MILIT ARY (4.5 V)
MIN MILITAR
Y (5.5 V)
0.20
- 55
- 40
- 20
0
25
40
70
80
100
125 X6094
Figure 32: Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations
TEMPERATURE (C)
Power
300 250 System Clock (MHz) 200 150 100 50 XC3000A--6 0 CLB Levels: 4 CLBs Gate Levels: (4-16) XC3100A-3
Power Distribution
Power for the FPGA is distributed through a grid to achieve high noise immunity and isolation between logic and I/O. Inside the FPGA, a dedicated VCC and ground ring surrounding the logic array provides power to the I/O drivers. An independent matrix of VCC and groundlines supplies the interior logic of the device. This power distribution grid provides a stable supply and ground for all internal logic, providing the external package power pins are all connected and appropriately decoupled. Typically a 0.1-F capacitor connected near the VCC and ground pins will provide adequate decoupling. Output buffers capable of driving the specified 4- or 8-mA loads under worst-case conditions may be capable of driving as much as 25 to 30 times that current in a best case. Noise can be reduced by minimizing external load capacitance and reducing simultaneous output transitions in the same direction. It may also be beneficial to locate heavily loaded output buffers near the ground pads. The I/O Block output buffers have a slew-limited mode which should be used where output rise and fall times are not speed critical. Slew-limited outputs maintain their dc drive capability, but generate less external reflections and internal noise.
3 CLBs (3-12)
2 CLBs (2-8)
1 CLB (1-4)
Toggle Rate
X7065
Figure 33: Clock Rate as a Function of Logic Complexity (Number of Combinational Levels between Flip-Flops)
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XC3000 Series Field Programmable Gate Arrays Dynamic Power Consumption
One CLB driving three local interconnects One global clock buffer and clock line One device output with a 50 pF load XC3042A 0.25 2.25 1.25 XC3042L 0.17 1.40 1.25 XC3142A 0.25 1.70 1.25 mW per MHz mW per MHz mW per MHz
Power Consumption
The Field Programmable Gate Array exhibits the low power consumption characteristic of CMOS ICs. For any design, the configuration option of TTL chip input threshold requires power for the threshold reference. The power required by the static memory cells that hold the configuration data is very low and may be maintained in a power-down mode. Typically, most of power dissipation is produced by external capacitive loads on the output buffers. This load and frequency dependent power is 25 W/pF/MHz per output. Another component of I/O power is the external dc loading on all output pins. Internal power dissipation is a function of the number and size of the nodes, and the frequency at which they change. In an FPGA, the fraction of nodes changing on a given clock is typically low (10-20%). For example, in a long binary counter, the total activity of all counter flip-flops is equivalent to that of only two CLB outputs toggling at the clock frequency. Typical global clock-buffer power is between 2.0 mW/MHz for the XC3020A and 3.5 mW/MHz for the XC3090A. The internal capacitive load is more a function of interconnect than fan-out. With a typical load of three general interconnect segments, each CLB output requires about 0.25 mW per MHz of its output frequency. Because the control storage of the FPGA is CMOS static memory, its cells require a very low standby current for data retention. In some systems, this low data retention current characteristic can be used as a method of preserving configurations in the event of a primary power loss. The FPGA has built in powerdown logic which, when activated, will disable normal operation of the device and retain only the configuration data. All internal operation is suspended and output buffers are placed in their high-impedance state with no pull-ups. Different from the XC3000 family which can be powered down to a current consumption of a few microamps, the XC3100A draws 5 mA, even in power-down. This makes power-down operation less meaningful. In contrast, ICCPD for the XC3000L is only 10 A. To force the FPGA into the Powerdown state, the user must pull the PWRDWN pin Low and continue to supply a retention voltage to the VCC pins. When normal power is restored, VCC is elevated to its normal operating voltage and PWRDWN is returned to a High. The FPGA resumes operation with the same internal sequence that occurs at the conclusion of configuration. Internal-I/O and logic-block storage elements will be reset, the outputs will become enabled and the DONE/PROG pin will be released. When VCC is shut down or disconnected, some power might unintentionally be supplied from an incoming signal driving an I/O pin. The conventional electrostatic input protection is implemented with diodes to the supply and ground. A positive voltage applied to an input (or output) will cause the positive protection diode to conduct and drive the VCC connection. This condition can produce invalid power conditions and should be avoided. A large series resistor might be used to limit the current or a bipolar buffer may be used to isolate the input signal.
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Pin Descriptions
Permanently Dedicated Pins
VCC Two to eight (depending on package type) connections to the positive V supply voltage. All must be connected. GND Two to eight (depending on package type) connections to ground. All must be connected. PWRDWN A Low on this CMOS-compatible input stops all internal activity, but retains configuration. All flip-flops and latches are reset, all outputs are 3-stated, and all inputs are interpreted as High, independent of their actual level. When PWDWN returns High, the FPGA becomes operational with DONE Low for two cycles of the internal 1-MHz clock. Before and during configuration, PWRDWN must be High. If not used, PWRDWN must be tied to VCC. RESET This is an active Low input which has three functions. Prior to the start of configuration, a Low input will delay the start of the configuration process. An internal circuit senses the application of power and begins a minimal time-out cycle. When the time-out and RESET are complete, the levels of the M lines are sampled and configuration begins. If RESET is asserted during a configuration, the FPGA is re-initialized and restarts the configuration at the termination of RESET. If RESET is asserted after configuration is complete, it provides a global asynchronous RESET of all IOB and CLB storage elements of the FPGA. CCLK During configuration, Configuration Clock is an output of an FPGA in Master mode or Peripheral mode, but an input in Slave mode. During Readback, CCLK is a clock input for shifting configuration data out of the FPGA. CCLK drives dynamic circuitry inside the FPGA. The Low time may, therefore, not exceed a few microseconds. When used as an input, CCLK must be "parked High". An internal pull-up resistor maintains High when the pin is not being driven. DONE/PROG (D/P) DONE is an open-drain output, configurable with or without an internal pull-up resistor of 2 to 8 k . At the completion of configuration, the FPGA circuitry becomes active in a synchronous order; DONE is programmed to go active High one cycle either before or after the outputs go active.
Once configuration is done, a High-to-Low transition of this pin will cause an initialization of the FPGA and start a reconfiguration. M0/RTRIG As Mode 0, this input is sampled on power-on to determine the power-on delay (214 cycles if M0 is High, 216 cycles if M0 is Low). Before the start of configuration, this input is again sampled together with M1, M2 to determine the configuration mode to be used. A Low-to-High input transition, after configuration is complete, acts as a Read Trigger and initiates a Readback of configuration and storage-element data clocked by CCLK. By selecting the appropriate Readback option when generating the bitstream, this operation may be limited to a single Readback, or be inhibited altogether. M1/RDATA As Mode 1, this input and M0, M2 are sampled before the start of configuration to establish the configuration mode to be used. If Readback is never used, M1 can be tied directly to ground or VCC. If Readback is ever used, M1 must use a 5-k resistor to ground or VCC, to accommodate the RDATA output. As an active-Low Read Data, after configuration is complete, this pin is the output of the Readback data.
User I/O Pins That Can Have Special Functions
M2 During configuration, this input has a weak pull-up resistor. Together with M0 and M1, it is sampled before the start of configuration to establish the configuration mode to be used. After configuration, this pin is a user-programmable I/O pin. HDC During configuration, this output is held at a High level to indicate that configuration is not yet complete. After configuration, this pin is a user-programmable I/O pin. LDC During Configuration, this output is held at a Low level to indicate that the configuration is not yet complete. After configuration, this pin is a user-programmable I/O pin. LDC is particularly useful in Master mode as a Low enable for an EPROM, but it must then be programmed as a High after configuration. INIT This is an active Low open-drain output with a weak pull-up and is held Low during the power stabilization and internal clearing of the configuration memory. It can be used to indicate status to a configuring microprocessor or, as a wired
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XC3000 Series Field Programmable Gate Arrays
AND of several slave mode devices, a hold-off signal for a master mode device. After configuration this pin becomes a user-programmable I/O pin. BCLKIN This is a direct CMOS level input to the alternate clock buffer (Auxiliary Buffer) in the lower right corner. XTL1 This user I/O pin can be used to operate as the output of an amplifier driving an external crystal and bias circuitry. XTL2 This user I/O pin can be used as the input of an amplifier connected to an external crystal and bias circuitry. The I/O Block is left unconfigured. The oscillator configuration is activated by routing a net from the oscillator buffer symbol output and by the MakeBits program. CS0, CS1, CS2, WS These four inputs represent a set of signals, three active Low and one active High, that are used to control configuration-data entry in the Peripheral mode. Simultaneous assertion of all four inputs generates a Write to the internal data buffer. The removal of any assertion clocks in the D0-D7 data. In Master-Parallel mode, WS and CS2 are the A0 and A1 outputs. After configuration, these pins are user-programmable I/O pins. RDY/BUSY During Peripheral Parallel mode configuration this pin indicates when the chip is ready for another byte of data to be written to it. After configuration is complete, this pin becomes a user-programmed I/O pin. RCLK During Master Parallel mode configuration, each change on the A0-15 outputs is preceded by a rising edge on RCLK, a redundant output signal. After configuration is complete, this pin becomes a user-programmed I/O pin. D0-D7 This set of eight pins represents the parallel configuration byte for the parallel Master and Peripheral modes. After configuration is complete, they are user-programmed I/O pins. A0-A15 During Master Parallel mode, these 16 pins present an address output for a configuration EPROM. After configuration, they are user-programmable I/O pins. DIN During Slave or Master Serial configuration, this pin is used as a serial-data input. In the Master or Peripheral configuration, this is the Data 0 input. After configuration is complete, this pin becomes a user-programmed I/O pin. DOUT During configuration this pin is used to output serial-configuration data to the DIN pin of a daisy-chained slave. After configuration is complete, this pin becomes a user-programmed I/O pin. TCLKIN This is a direct CMOS-level input to the global clock buffer. This pin can also be configured as a user programmable I/O pin. However, since TCLKIN is the preferred input to the global clock net, and the global clock net should be used as the primary clock source, this pin is usually the clock input to the chip.
7
Unrestricted User I/O Pins
I/O An I/O pin may be programmed by the user to be an Input or an Output pin following configuration. All unrestricted I/O pins, plus the special pins mentioned on the following page, have a weak pull-up resistor that becomes active as soon as the device powers up, and stays active until the end of configuration.
Note: Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a weak pull-up resistor.
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XC3000 Series Field Programmable Gate Arrays Pin Functions During Configuration
Configuration Mode SLAVE SERIAL <1:1:1> POWR DWN (I) M1 (HIGH) (I) M0 (HIGH) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT* GND RESET (I) DONE MASTERSERIAL <0:0:0> POWER DWN (I) M1 (LOW) (I) M0 (LOW) (I) M2 (LOW) (I) HDC (HIGH) LDC (LOW) INIT* GND RESET (I) DONE MASTERHIGH <1:1:0> POWER DWN (I) M1 (HIGH) (I) M0 (LOW) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT* GND RESET (I) DONE DATA 7 (I) DATA 6 (I) DATA 5 (I) DATA 4 (I) DATA 3 (I) DATA 2 (I) DATA 1 (I) RCLK DATA 0 (I) DOUT CCLK (O) A0 A1 A2 A3 A15 A4 A14 A5 A13 A6 A12 A7 A11 A8 A10 A9 MASTERLOW <1:0:0> POWER DWN (I) M1 (LOW) (I) M0 (LOW) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT* GND RESET (I) DONE DATA 7 (I) 30 DATA 6 (I) DATA 5 (I) CS0 (I) DATA 4 (I) DATA 3 (I) CS1 (I) DATA 2 (I) DATA 1 (I) RDY/BUSY DIN (I) DOUT CCLK (I) DIN (I) DOUT CCLK (O) DATA 0 (I) DOUT CCLK (O) WS (I) CS2 (I) DATA 2 (I) DATA 1 (I) RCLK DATA 0 (I) DOUT CCLK (O) A0 A1 A2 A3 A15 A4 A14 A5 A13 A6 A12 A7 A11 A8 A10 A9 5 6 7 9 10 11 12 13 14 15 16 38 39 40 DATA 4 (I) DATA 3 (I) DATA 6 (I) DATA 5 (I)
***
**
****
User Function POWER DWN (1) RDATA RTRIG (I) I/O I/O I/O I/O GND XTL2 OR I/O RESET (I) PROGRAM (I) I/O XTL1 OR I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CCLK (I) I/O I/O I/O I/O 5 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O All Others XC3x20A etc. X X X X X X X X X X X X X X XC3x30A etc. XC3x42A etc. XC3x64A etc. XC3x90A etc. XC3195A
PERIPH <1:0:1> POWER DWN (I) M1 (LOW) (I) M0 (HIGH) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT* GND RESET (I) DONE DATA 7 (I)
100 44 64 68 84 84 100 VQFP 132 144 160 175 176 208 PLCC VQFP PLCC PLCC PGA PQFP TQFP PGA TQFP PQFP PGA TQFP PQFP
7 16 17 18 19 20 22 23 26 27 28
17 31 32 33 34 36 40 41 47 48 49 50 51 52 53 54 55 57 58 59 60 61 62 63 64 1 2 3 4
10 25 26 27 28 30 34 35 43 44 45 46 47 48 49 50 51 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 2 3 4 5 6 7 8 9 X
12 31 32 33 34 36 42 43 53 54 55 56 57 58 60 61 62 65 66 67 70 71 72 73 74 75 76 77 78 81 82 83 84 2 3 4 5 8 9 10 11 X X X X** X**
B2 J2 L1 K2 K3 L3 K6 J6 L11 K10 J10 K11 J11 H10 F10 G10 G11 F11 E11 E10 D10 C11 B11 C10 A11 B10 B9 A10 A9 B6 B7 A7 C7 A6 A5 B5 C5 A3 A2 B3 A1 X X X
29 52 54 56 57 59 65 66 76 78 80 81 82 83 87 88 89 92 93 94 98 99 100 1 2 5 6 8 9 12 13 14 15 17 18 19 20 23 24 25 26 X X X
26 49 51 53 54 56 62 63 73 75 77 78 79 80 84 85 86 89 90 91 95 96 97 98 99 2 3 5 6 9 10 11 12 14 15 16 17 20 21 22 26
A1 B13 A14 C13 B14 D14 G14 H12 M13 P14 N13 M12 P13 N11 M9 N9 N8 N7 P6 M6 M5 N4 N2 M3 P1 M2 N1 L2 L1 K1 J2 H1 H2 G2 G1 F2 E1 D1 D2 B1 C2
1 36 38 40 41 45 53 55 69 71 73 74 75 78 84 85 88 92 93 96 102 103 106 107 108 111 112 115 116 119 120 123 124 128 129 133 134 137 138 141 142
159 40 42 44 45 49 59 61 76 78 80 81 82 86 92 93 96 102 103 106 114 115 119 120 121 124 125 128 129 132 133 136 137 141 142 147 148 151 152 155 156
B2 B14 B15 C15 E14 D16 H15 J14 P15 R15 R14 N13 T14 P12 T11 R10 R9 P8 R8 R7 R5 P5 R3 N4 R2 P2 M3 P1 N1 M1 L2 K2 K1 H2 H1 F2 E1 D1 C1 E3 C2
1 45 47 49 50 54 65 67 85 87 89 90 91 96 102 103 108 112 113 118 124 125 130 131 132 135 136 140 141 146 147 150 151 156 157 164 165 169 170 173 174
3 48 50 56 57 61 77 79 100 102 107 109 110 115 122 123 128 132 133 138 145 146 151 152 153 161 162 165 166 172 173 178 179 184 185 192 193 199 200 203 204
X
X
X
Notes:
X**
* (I) ** *** ****
Generic I/O pins are not shown. For a detailed description of the configuration modes, see page 25 through page 34. For pinout details, see page 65 through page 76. Represents a weak pull-up before and during configuration. INIT is an open drain output during configuration. Represents an input. Pin assignment for the XC3064A/XC3090A and XC3195A differ from those shown. Peripheral mode and master parallel mode are not supported in the PC44 package. Pin assignments for the XC3195A PQ208 differ from those shown. Pin assignments of PGA Footprint PLCC sockets and PGA packages are not identical. The information on this page is provided as a convenient summary. For detailed pin descriptions, see the preceding two pages. Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a weak pull-up resistor.
Note:
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XC3000 Series Field Programmable Gate Arrays
XC3000A Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision.
XC3000A Operating Conditions
Symbol VCC VIHT VILT VIHC VILC TIN Note: Description Supply voltage relative to GND Commercial 0C to +85C junction Supply voltage relative to GND Industrial -40C to +100C junction High-level input voltage -- TTL configuration Low-level input voltage -- TTL configuration High-level input voltage -- CMOS configuration Low-level input voltage -- CMOS configuration Input signal transition time Min 4.75 4.5 2.0 0 70% 0 Max 5.25 5.5 VCC 0.8 100% 20% 250 Units V V V V VCC VCC ns
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per C.
XC3000A DC Characteristics Over Operating Conditions
Symbol VOH VOL VOH VOL VCCPD ICCPD Description High-level output voltage (@ IOH = -4.0 mA, VCC min) Low-level output voltage (@ IOL = 4.0 mA, VCC min) High-level output voltage (@ IOH = -4.0 mA, VCC min) Low-level output voltage (@ IOL = 4.0 mA, VCC min) Power-down supply voltage (PWRDWN must be Low) Power-down supply current (VCC(MAX) @ TMAX) Min 3.86 3.76 0.40 2.30 3020A 3030A 3042A 3064A 3090A 100 160 240 340 500 500 10 +10 Max 0.40 Units V V V V V A A A A A A A A
Commercial Industrial
7
ICCO IIL
CIN
IRIN IRLL
Quiescent FPGA supply current in addition to ICCPD Chip thresholds programmed as CMOS levels Chip thresholds programmed as TTL levels Input Leakage Current Input capacitance, all packages except PGA175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 Input capacitance, PGA 175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 Pad pull-up (when selected) @ VIN = 0 V3 Horizontal Longline pull-up (when selected) @ logic Low
-10
10 15
pF pF
0.02
16 20 0.17 3.4
pF pF mA mA
Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the FPGA
device configured with a tie option. 2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source may not exceed 100 mA per VCC pin. The number of ground pins varies from the XC3020A to the XC3090A. 3. Not tested. Allow an undriven pin to float High. For any other purposes use an external pull-up.
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XC3000 Series Field Programmable Gate Arrays
XC3000A Absolute Maximum Ratings
Symbol VCC VIN VTS TSTG TSOL TJ Note: Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) Junction temperature plastic Junction temperature ceramic -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +125 +150 Units V V V C C C C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
XC3000A Global Buffer Switching Characteristics Guidelines
Description Global and Alternate Clock Distribution1 Either: Normal IOB input pad through clock buffer to any CLB or IOB clock input Or: Fast (CMOS only) input pad through clock buffer to any CLB or IOB clock input TBUF driving a Horizontal Longline (L.L.)1 I to L.L. while T is Low (buffer active) T to L.L. active and valid with single pull-up resistor T to L.L. active and valid with pair of pull-up resistors T to L.L. High with single pull-up resistor T to L.L. High with pair of pull-up resistors BIDI Bidirectional buffer delay Speed Grade Symbol -7 Max -6 Max Units
TPID TPIDC TIO TON TON TPUS TPUF TBIDI
7.5 6.0 4.5 9.0 11.0 16.0 10.0 1.7
7.0 5.7 4.0 8.0 10.0 14.0 8.0 1.5
ns ns ns ns ns ns ns ns
Note: 1. Timing is based on the XC3042A, for other devices see timing calculator.
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XC3000 Series Field Programmable Gate Arrays XC3000A CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used in the simulator. Speed Grade Symbol -7 Min Max Min -6 Max Units
Description Combinatorial Delay Logic Variables A, B, C, D, E, to outputs X or Y FG Mode F and FGM Mode
1
TILO
5.1 5.6 4.5
4.1 4.6 4.0
ns ns ns
Sequential delay Clock k to outputs X or Y Clock k to outputs X or Y when Q is returned through function generators F or G to drive X or Y FG Mode F and FGM Mode Set-up time before clock K Logic Variables A, B, C, D, E FG Mode F and FGM Mode Data In DI Enable Clock EC Hold Time after clock K Logic Variables A, B, C, D, E Data In DI2 Enable Clock EC Clock Clock High time Clock Low time Max. flip-flop toggle rate Reset Direct (RD) RD width delay from RD to outputs X or Y Global Reset (RESET Pad)1 RESET width (Low) delay from RESET pad to outputs X or Y
8
TCKO
TQLO
9.5 10.0
8.0 8.5
ns ns
2 4 6 3 5 7 11 12
TICK TDICK TECCK TCKI TCKDI TCKEC TCH TCL FCLK TRPW TRIO TMRW TMRQ
4.5 5.0 4.0 4.5 0 1.0 2.0 4.0 4.0 113.0 6.0 6.0 16.0 19.0
3.5 4.0 3.0 4.0 0 1.0 2.0 3.5 3.5 135.0 5.0 5.0 14.0 17.0
ns ns ns ns
7
ns ns ns ns ns MHz ns ns ns ns
13 9
Notes: 1. Timing is based on the XC3042A, for other devices see timing calculator.
2. The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data In hold time requirement (TCKDI, #5) of any CLB on the same die.
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XC3000 Series Field Programmable Gate Arrays XC3000A CLB Switching Characteristics Guidelines (continued)
CLB Output (X, Y) (Combinatorial) 1 CLB Input (A,B,C,D,E) 2 CLB Clock 12 TCL 4 CLB Input (Direct In) 6 CLB Input (Enable Clock) 8 CLB Output (Flip-Flop) TCKO T ECCK 7 TCKEC TDICK 11 T CH 5 TCKDI T ICK 3 T CKI T ILO
CLB Input (Reset Direct) 13 TRPW 9 T RIO CLB Output (Flip-Flop)
X5424
T
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XC3000 Series Field Programmable Gate Arrays XC3000A IOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used in the simulator. Speed Grade Symbol 3 4 1 7 7 10 10 9 9 8 8 5 6 11 12 TPID TPTG TIKRI TPICK TOKPO TOKPO TOPF TOPS TTSHZ TTSHZ TTSON TTSON TOOK TOKO TIOH TIOL FCLK TRRI TRPO TRPO 8.0 0 4.0 4.0 113.0 24.0 33.0 43.0 14.0 8.0 18.0 6.0 16.0 10.0 20.0 11.0 21.0 7.0 0 3.5 3.5 135.0 23.0 29.0 37.0 -7 Min Max 4.0 15.0 3.0 12.0 7.0 15.0 5.0 13.0 9.0 12.0 10.0 18.0 Min -6 Max 3.0 14.0 2.5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns
Description Propagation Delays (Input) Pad to Direct In (I) Pad to Registered In (Q) with latch transparent Clock (IK) to Registered In (Q) Set-up Time (Input) Pad to Clock (IK) set-up time Propagation Delays (Output) Clock (OK) to Pad (fast) same (slew rate limited) Output (O) to Pad (fast) same (slew-rate limited) 3-state to Pad begin hi-Z (fast) same (slew-rate limited) 3-state to Pad active and valid (fast) same (slew -rate limited) Set-up and Hold Times (Output) Output (O) to clock (OK) set-up time Output (O) to clock (OK) hold time Clock Clock High time Clock Low time Max. flip-flop toggle rate Global Reset Delays (based on XC3042A) RESET Pad to Registered In (Q) (fast) RESET Pad to output pad (slew-rate limited)
7
13 15 15
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output rise/fall times are approximately four times longer. 2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal pull-up resistor or alternatively configured as a driven output or driven from an external source. 3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized. 4. TPID, TPTG, and TPICK are 3 ns higher for XTL2 when the pin is configured as a user input.
November 9, 1998 (Version 3.1)
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XC3000 Series Field Programmable Gate Arrays XC3000A IOB Switching Characteristics Guidelines (continued)
I/O Block (I) 3 I/O Pad Input 1 I/O Clock (IK/OK) 12 TIOL I/O Block (RI) 4 RESET 5 I/O Block (O) 10 TOP I/O Pad Output (Direct) 7 I/O Pad Output (Registered) TOKPO TOOK 6 TOKO 15 TRPO TIKRI 13 TRRI 11 TIOH T PICK T PID
I/O Pad TS 8 I/O Pad Output
X5425
TTSON
9
T TSHZ
Vcc PROGRAM-CONTROLLED MEMORY CELLS
OUT INVERT
3-STATE INVERT
OUTPUT SELECT
SLEW RATE
PASSIVE PULL UP
3- STATE (OUTPUT ENABLE)
T
OUT
O
D
Q
FLIP FLOP
OUTPUT BUFFER
I/O PAD R DIRECT IN REGISTERED IN I Q QD FLIP FLOP or LATCH R OK IK (GLOBAL RESET) TTL or CMOS INPUT THRESHOLD
CK1
CK2 PROGRAM CONTROLLED MULTIPLEXER = PROGRAMMABLE INTERCONNECTION POINT or PIP
X3029
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XC3000 Series Field Programmable Gate Arrays
XC3000L Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision.
XC3000L Operating Conditions
Symbol VCC VIH VIL TIN Description Supply voltage relative to GND Commercial 0C to +85C junction High-level input voltage -- TTL configuration Low-level input voltage -- TTL configuration Input signal transition time Min 3.0 2.0 -0.3 Max 3.6 VCC+0.3 0.8 250 Units V V V ns
Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per C.
2. Although the present (1996) devices operate over the full supply voltage range from 3.0 to 5.25 V, Xilinx reserves the right to restrict operation to the 3.0 to 3.6 V range later, when smaller device geometries might preclude operation at 5V. Operating conditions are guaranteed in the 3.0 - 3.6 V VCC range.
XC3000L DC Characteristics Over Operating Conditions
Symbol VOH VOL VOH VOL VCCPD ICCPD ICCO IIL Description High-level output voltage (@ IOH = -4.0 mA, VCC min) Low-level output voltage (@ IOL = 4.0 mA, VCC min) High-level output voltage (@ IOH = -4.0 mA, VCC min) Low-level output voltage (@ IOL = 4.0 mA, VCC min) Power-down supply voltage (PWRDWN must be Low) Power-down supply current (VCC(MAX) @ TMAX) Quiescent FPGA supply current in addition to ICCPD1 Chip thresholds programmed as CMOS levels Input Leakage Current Input capacitance, all packages except PGA175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 Input capacitance, PGA 175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 Pad pull-up (when selected) @ VIN = 0 V3 Horizontal Longline pull-up (when selected) @ logic Low Min 2.40 VCC -0.2 0.2 2.30 10 20 +10 Max 0.40 Units V V V V V A A A
7
-10
CIN
10 15
pF pF
IRIN IRLL
0.01
15 20 0.17 2.50
pF pF mA mA
Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the FPGA
device configured with a tie option. ICCO is in addition to ICCPD. 2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source may not exceed 100 mA per VCC pin. The number of ground pins varies from the XC3020L to the XC3090L. 3. Not tested. Allows an undriven pin to float High. For any other purpose, use an external pull-up.
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XC3000 Series Field Programmable Gate Arrays XC3000L Absolute Maximum Ratings
Symbol VCC VIN VTS TSTG TSOL TJ Note: Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) Junction temperature plastic Junction temperature ceramic -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +125 +150 Units V V V C C C C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
XC3000L Global Buffer Switching Characteristics Guidelines
Description Global and Alternate Clock Distribution1 Either: Normal IOB input pad through clock buffer to any CLB or IOB clock input Or: Fast (CMOS only) input pad through clock buffer to any CLB or IOB clock input TBUF driving a Horizontal Longline (L.L.)1 I to L.L. while T is Low (buffer active) T to L.L. active and valid with single pull-up resistor T to L.L. High with single pull-up resistor BIDI Bidirectional buffer delay Speed Grade Symbol -8 Max Units
TPID TPIDC TIO TON TPUS TBIDI
9.0 7.0 5.0 12.0 24.0 2.0
ns ns ns ns ns ns
Notes: 1. Timing is based on the XC3042A, for other devices see timing calculator. 2. The use of two pull-up resistors per Longline, available on other XC3000 devices, is not a valid option for XC3000L devices.
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XC3000 Series Field Programmable Gate Arrays XC3000L CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used in the simulator. Speed Grade Symbol -8 Min Max Units
Description Combinatorial Delay Logic Variables A, B, C, D, E, to outputs X or Y FG Mode F and FGM Mode
1
TILO
6.7 7.5 7.5
ns ns ns
Sequential delay Clock k to outputs X or Y Clock k to outputs X or Y when Q is returned through function generators F or G to drive X or Y FG Mode F and FGM Mode Set-up time before clock K Logic Variables A, B, C, D, E FG Mode F and FGM Mode Data In DI Enable Clock EC Hold Time after clock K Logic Variables A, B, C, D, E Data In DI2 Enable Clock EC Clock Clock High time Clock Low time Max. flip-flop toggle rate Reset Direct (RD) RD width delay from RD to outputs X or Y Global Reset (RESET Pad)1 RESET width (Low) delay from RESET pad to outputs X or Y Notes: 1. Timing is based on the XC3042L, for other devices see timing calculator.
8
TCKO
TQLO
14.0 14.8
ns ns
2 4 6 3 5 7 11 12
TICK TDICK TECCK TCKI TCKDI TCKEC TCH TCL FCLK TRPW TRIO TMRW TMRQ
5.0 5.8 5.0 6.0 0 2.0 2.0 5.0 5.0 80.0 7.0 7.0 16.0 23.0
ns ns ns ns
7
ns ns ns ns ns MHz ns ns ns ns
13 9
2. The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data In hold time requirement (TCKDI, #5) of any CLB on the same die.
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XC3000 Series Field Programmable Gate Arrays XC3000L CLB Switching Characteristics Guidelines (continued)
CLB Output (X, Y) (Combinatorial) 1 CLB Input (A,B,C,D,E) 2 CLB Clock 12 TCL 4 CLB Input (Direct In) 6 CLB Input (Enable Clock) 8 CLB Output (Flip-Flop) TCKO T ECCK 7 TCKEC TDICK 11 T CH 5 TCKDI T ICK 3 T CKI T ILO
CLB Input (Reset Direct) 13 TRPW 9 T RIO CLB Output (Flip-Flop)
X5424
T
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XC3000 Series Field Programmable Gate Arrays XC3000L IOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used in the simulator. Speed Grade Symbol 3 4 1 7 7 10 10 9 9 8 8 5 6 11 12 TPID TPTG TIKRI TPICK TOKPO TOKPO TOPF TOPS TTSHZ TTSHZ TTSON TTSON TOOK TOKO TIOH TIOL FCLK TRRI TRPO TRPO 12.0 0 5.0 5.0 80.0 25.0 35.0 51.0 22.0 12.0 28.0 9.0 25.0 12.0 28.0 16.0 32.0 -8 Min Max 5.0 24.0 6.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns
Description Propagation Delays (Input) Pad to Direct In (I) Pad to Registered In (Q) with latch transparent Clock (IK) to Registered In (Q) Set-up Time (Input) Pad to Clock (IK) set-up time Propagation Delays (Output) Clock (OK) to Pad (fast) same (slew rate limited) Output (O) to Pad (fast) same (slew-rate limited) 3-state to Pad begin hi-Z (fast) same (slew-rate limited) 3-state to Pad active and valid (fast) same (slew -rate limited) Set-up and Hold Times (Output) Output (O) to clock (OK) set-up time Output (O) to clock (OK) hold time Clock Clock High time Clock Low time Max. flip-flop toggle rate Global Reset Delays (based on XC3042L) (Q) RESET Pad to Registered In (fast) RESET Pad to output pad (slew-rate limited)
7
13 15 15
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output
rise/fall times are approximately four times longer. 2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal pull-up resistor or alternatively configured as a driven output or driven from an external source. 3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized. 4. TPID, TPTG, and TPICK are 3 ns higher for XTL2 when the pin is configured as a user input.
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XC3000 Series Field Programmable Gate Arrays XC3000L IOB Switching Characteristics Guidelines (continued)
I/O Block (I) 3 I/O Pad Input 1 I/O Clock (IK/OK) 12 TIOL I/O Block (RI) 4 RESET 5 I/O Block (O) 10 TOP I/O Pad Output (Direct) 7 I/O Pad Output (Registered) TOKPO TOOK 6 TOKO 15 TRPO TIKRI 13 TRRI 11 TIOH T PICK T PID
I/O Pad TS 8 I/O Pad Output
X5425
TTSON
9
T TSHZ
Vcc PROGRAM-CONTROLLED MEMORY CELLS
OUT INVERT
3-STATE INVERT
OUTPUT SELECT
SLEW RATE
PASSIVE PULL UP
3- STATE (OUTPUT ENABLE)
T
OUT
O
D
Q
FLIP FLOP
OUTPUT BUFFER
I/O PAD R DIRECT IN REGISTERED IN I Q QD FLIP FLOP or LATCH R OK IK (GLOBAL RESET) TTL or CMOS INPUT THRESHOLD
CK1
CK2 PROGRAM CONTROLLED MULTIPLEXER = PROGRAMMABLE INTERCONNECTION POINT or PIP
X3029
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XC3000 Series Field Programmable Gate Arrays
XC3100A Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision.
XC3100A Operating Conditions
Symbol VCC VIHT VILT VIHC VILC TIN Note: Description Supply voltage relative to GND Commercial 0C to +85C junction Supply voltage relative to GND Industrial -40C to +100C junction High-level input voltage -- TTL configuration Low-level input voltage -- TTL configuration High-level input voltage -- CMOS configuration Low-level input voltage -- CMOS configuration Input signal transition time Min 4.25 4.5 2.0 0 70% 0 Max 5.25 5.5 VCC 0.8 100% 20% 250 Units V V V V VCC VCC ns
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per C.
XC3100A DC Characteristics Over Operating Conditions
Symbol VOH VOL VOH VOL VCCPD ICCO IIL Description High-level output voltage (@ IOH = -8.0 mA, VCC min) Low-level output voltage (@ IOL = 8.0 mA, VCC min) High-level output voltage (@ IOH = -8.0 mA, VCC min) Low-level output voltage (@ IOL = 8.0 mA, VCC min) Power-down supply voltage (PWRDWN must be Low) Quiescent LCA supply current in addition to ICCPD1 Chip thresholds programmed as CMOS levels Chip thresholds programmed as TTL levels Input Leakage Current Input capacitance, all packages except PGA175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 Input capacitance, PGA 175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 Pad pull-up (when selected) @ VIN = 0 V3 Horizontal Longline pull-up (when selected) @ logic Low Min 3.86 3.76 0.40 2.30 8 14 +10 Max 0.40 Units V V V V V mA mA A
Commercial Industrial
7
-10
CIN
10 15
pF pF
IRIN IRLL
0.02 0.20
15 20 0.17 2.80
pF pF mA mA
Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the LCA
device configured with a tie option. 2. Total continuous output sink current may not exceed 100 mA per ground pin. The number of ground pins varies from two for the XC3120A in the PC84 package, to eight for the XC3195A in the PQ208 package. 3. Not tested. Allows an undriven pin to float High. For any other purpose, use an external pull-up.
November 9, 1998 (Version 3.1)
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XC3000 Series Field Programmable Gate Arrays XC3100A Absolute Maximum Ratings
Symbol VCC VIN VTS TSTG TSOL TJ Note: Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) Junction temperature plastic Junction temperature ceramic -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +125 +150 Units V V V C C C C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
XC3100A Global Buffer Switching Characteristics Guidelines
Description Global and Alternate Clock Distribution1 Either: Normal IOB input pad through clock buffer to any CLB or IOB clock input Or: Fast (CMOS only) input pad through clock buffer to any CLB or IOB clock input TBUF driving a Horizontal Longline (L.L.)1 I to L.L. while T is Low (buffer active) (XC3100) (XC3100A) T to L.L. active and valid with single pull-up resistor T to L.L. active and valid with pair of pull-up resistors T to L.L. High with single pull-up resistor T to L.L. High with pair of pull-up resistors BIDI Bidirectional buffer delay Speed Grade -4 Symbol Max -3 Max -2 Max -1 Max -09 Max Units
TPID TPIDC TIO TIO TON TON TPUS TPUF TBIDI
6.5 5.1 3.7 3.6 5.0 6.5 13.5 10.5 1.2
5.6 4.3 3.1 3.1 4.2 5.7 11.4 8.8 1.0
4.7 3.7
4.3 3.5
3.9 3.1
ns ns ns ns ns ns ns ns ns
3.1 4.2 5.7 11.4 8.1 0.9
2.9 4.0 5.5 10.4 7.1 0.85
2.1 3.1 4.6 8.9 5.9 0.75
Prelim
Note:
1. Timing is based on the XC3142A, for other devices see timing calculator. The use of two pull-up resistors per longline, available on other XC3000 devices, is not a valid design option for XC3100A devices.
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XC3000 Series Field Programmable Gate Arrays XC3100A CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used in the simulator.
Speed Grade Description Symbol Combinatorial Delay Logic Variables A, B, C, D, E, 1 TILO to outputs X or Y Sequential delay Clock k to outputs X or Y 8 TCKO Clock k to outputs X or Y when Q is returned through function generators F or G to drive X or Y TQLO Set-up time before clock K Logic Variables A, B, C, D, E Data In DI Enable Clock EC Reset Direct inactive RD Hold Time after clock K Logic Variables A, B, C, D, E Data In DI Enable Clock EC Clock Clock High time Clock Low time Max. flip-flop toggle rate Reset Direct (RD) RD width delay from RD to outputs X or Y Global Reset (RESET Pad)1 RESET width (Low) (XC3142A) delay from RESET pad to outputs X or Y 2 TICK 4 TDICK 6 TECCK Min -4 Max 3.3 Min -3 Max 2.7 Min -2 Max 2.2 Min -1 Max 1.75 -09 Min Max 1.5 Units ns
2.5
2.1
1.7
1.4
1.25
ns
5.2 2.5 1.6 3.2 1.0 0 1.0 0.8 2.0 2.0 227 3.2 3.7 14.0 14.0 12.0 2.1 1.4 2.7 1.0 0 0.9 0.7 1.6 1.6 270 2.7
4.3 1.8 1.3 2.5 1.0 0 0.9 0.7 1.3 1.3 323 2.3 3.1 12.0 12.0
3.5 1.7 1.2 2.3 1.0 0 0.8 0.6 1.3 1.3 323 2.3 2.7 12.0 12.0
3.1 1.5 1.0 2.05 1.0 0 0.7 0.55 1.3 1.3 370 2.05 2.4 12.0 12.0
2.7
ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns
3 TCKI 5 TCKDI 7 TCKEC 11 12 TCH TCL FCLK
7
13 TRPW 9 TRIO TMRW TMRQ
2.15
12.0 Prelim
Notes: 1. The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold time requirement (TCKDI, #5) of any CLB on the same die. 2. TILO, TQLO and TICK are specified for 4-input functions. For 5-input functions or base FGM functions, each of these specifications for the XC3100A family increases by 0.50 ns (-5), 0.42 ns (-4) and 0.35 ns (-3), 0.35 ns (-2), 0.30 ns (-1), and 0.30 ns (-09).
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XC3000 Series Field Programmable Gate Arrays XC3100A CLB Switching Characteristics Guidelines (continued)
CLB Output (X, Y) (Combinatorial) 1 CLB Input (A,B,C,D,E) 2 CLB Clock 12 TCL 4 CLB Input (Direct In) 6 CLB Input (Enable Clock) 8 CLB Output (Flip-Flop) TCKO T ECCK 7 TCKEC TDICK 11 T CH 5 TCKDI T ICK 3 T CKI T ILO
CLB Input (Reset Direct) 13 TRPW 9 T RIO CLB Output (Flip-Flop)
X5424
T
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XC3000 Series Field Programmable Gate Arrays XC3100A IOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used in the simulator.
Speed Grade Description Symbol Propagation Delays (Input) Pad to Direct In (I) 3 TPID Pad to Registered In (Q) TPTG with latch transparent(XC3100A)Clock (IK) to Registered In (Q) 4 TIKRI Set-up Time (Input) Pad to Clock (IK) set-up time XC3120A, XC3130A XC3142A XC3164A XC3190A XC3195A Propagation Delays (Output) Clock (OK) to Pad (fast) same (slew rate limited) Output (O) to Pad (fast) same (slew-rate limited) (XC3100A) 3-state to Pad begin hi-Z (fast) same (slew-rate limited) 3-state to Pad active and valid (fast) (XC3100A) same (slew -rate limited) Set-up and Hold Times (Output) Output (O) to clock (OK) set-up time (XC3100A) Output (O) to clock (OK) hold time Clock Clock High time Clock Low time Max. flip-flop toggle rate Global Reset Delays RESET Pad to Registered In (Q) (XC3142A) (XC3190A) RESET Pad to output pad (fast) (slew-rate limited) Min -4 Max 2.5 12.0 2.5 Min -3 Max 2.2 11.0 2.2 Min -2 Max 2.0 11.0 1.9 Min -1 Max 1.7 10.0 1.7 -09 Min Max 1.55 9.2 1.55 Units ns ns ns
1
TPICK
10.6 10.7 11.0 11.2 11.6 5.0 12.0 3.7 11.0 6.2 6.2 10.0 17.0
9.4 9.5 9.7 9.9 10.3 4.4 10.0 3.3 9.0 5.5 5.5 9.0 15.0
8.9 9.0 9.2 9.4 9.8 3.7 9.7 3.0 8.7 5.0 5.0 8.5 14.2
8.0 8.1 8.3 8.5 8.9 3.4 8.4 3.0 8.0 4.5 4.5 6.5 11.5
7.2 7.3 7.5 7.7 8.1 3.3 6.9 2.9 6.5 4.05 4.05 5.0 8.6
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
7 TOKPO 7 TOKPO 10 TOPF 10 TOPS 9 9 TTSHZ TTSHZ
7
8 TTSON 8 TTSON
5 6 11 12
TOOK TOKO TIOH TIOL FCLK
4.5 0 2.0 2.0 227 1.6 1.6 270
3.6 0 1.3 1.3 323
3.2 0 1.3 1.3 323
2.9
ns ns ns ns MHz
1.3 1.3 370
13
TRRI
15 TRPO 15 TRPO
15.0 25.5 20.0 27.0
13.0 21.0 17.0 23.0
13.0 21.0 17.0 23.0
13.0 21.0 17.0 22.0
14.4 21.0 17.0 21.0 Preliminary
ns ns ns ns
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads, see
XAPP024. Typical slew rate limited output rise/fall times are approximately four times longer. 2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal pull-up resistor or alternatively configured as a driven output or driven from an external source. 3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized. 4. TPID, TPTG, and TPICK are 3 ns higher for XTL2 when the pin is configured as a user input.
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XC3000 Series Field Programmable Gate Arrays XC3100A IOB Switching Characteristics Guidelines (continued)
I/O Block (I) 3 I/O Pad Input 1 I/O Clock (IK/OK) 12 TIOL I/O Block (RI) 4 RESET 5 I/O Block (O) 10 TOP I/O Pad Output (Direct) 7 I/O Pad Output (Registered) TOKPO TOOK 6 TOKO 15 TRPO TIKRI 13 TRRI 11 TIOH T PICK T PID
I/O Pad TS 8 I/O Pad Output
X5425
TTSON
9
T TSHZ
Vcc PROGRAM-CONTROLLED MEMORY CELLS
OUT INVERT
3-STATE INVERT
OUTPUT SELECT
SLEW RATE
PASSIVE PULL UP
3- STATE (OUTPUT ENABLE)
T
OUT
O
D
Q
FLIP FLOP
OUTPUT BUFFER
I/O PAD R DIRECT IN REGISTERED IN I Q QD FLIP FLOP or LATCH R OK IK (GLOBAL RESET) TTL or CMOS INPUT THRESHOLD
CK1
CK2 PROGRAM CONTROLLED MULTIPLEXER = PROGRAMMABLE INTERCONNECTION POINT or PIP
X3029
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XC3000 Series Field Programmable Gate Arrays
XC3100L Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision.
XC3100L Operating Conditions
Symbol VCC VIH VIL TIN Description Supply voltage relative to GND Commercial 0C to +85C junction High-level input voltage Low-level input voltage Input signal transition time Min 3.0 2.0 -0.3 Max 3.6 VCC + 0.3 0.8 250 Units V V V ns
Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per C.
2. Although the present (1996) devices operate over the full supply voltage range from 3.0 V to 5.25 V, Xilinx reserves the right to restrict operation to the 3.0 and 3.6 V range later, when smaller device geometries might preclude operation @ 5 V. Operating conditions are guaranteed in the 3.0 - 3.6 V VCC range.
XC3100L DC Characteristics Over Operating Conditions
Symbol VOH VOL VCCPD ICCO IIL CIN IRIN Description High-level output voltage (@ IOH = -4.0 mA, VCC min) High-level output voltage (@ IOH = -100.0 A, VCC min) Low-level output voltage (@ IOH = 4.0 mA, VCC min) Low-level output voltage (@ IOH = +100.0 A, VCC min) Power-down supply voltage (PWRDWN must be Low) Quiescent FPGA supply current Chip thresholds programmed as CMOS levels1 Input Leakage Current Input capacitance (sample tested) All pins except XTL1 and XTL2 XTL1 and XTL2 Pad pull-up (when selected) @ VIN = 0 V 3 Horizontal long line pull-up (when selected) @ logic Low Min 2.4 VCC -0.2 Max Units V V V V V mA A
0.40 0.2 2.30 1.5 -10 +10
7
IRLL
0.02 0.20
10 15 0.17 2.80
pF pF mA mA
Notes: 1. With no output current loads, no active input or long line pull-up resistors, all package pins at VCC or GND, and the FPGA
configured with a tie option. 2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source current may not exceed 100 mA per VCC pin. The number of ground pins varies from the XC3142L to the XC3190L. 3. Not tested. Allows undriven pins to float High. For any other purpose, use an external pull-up.
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XC3000 Series Field Programmable Gate Arrays XC3100L Absolute Maximum Ratings
Symbol VCC VIN VTS TSTG TSOL TJ Note: Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) Junction temperature plastic Junction temperature ceramic -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +125 +150 Units V V V C C C C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
XC3100L Global Buffer Switching Characteristics Guidelines
Description Global and Alternate Clock Distribution1 Either:Normal IOB input pad through clock buffer to any CLB or IOB clock input Or: Fast (CMOS only) input pad through clock buffer to any CLB or IOB clock input TBUF driving a Horizontal Longline (L.L.)1 I to L.L. while T is Low (buffer active) T to L.L. active and valid with single pull-up resistor T to L.L. High with single pull-up resistor BIDI Bidirectional buffer delay Speed Grade Symbol -3 Max -2 Max Units
TPID TPIDC TIO TON TPUS TBIDI
5.6 4.3 3.1 4.2 11.4 1.0 Advance
4.7 3.7 3.1 4.2 11.4 0.9
ns ns ns ns ns ns
Notes: 1. Timing is based on the XC3142L, for other devices see timing calculator.
2. The use of two pull-up resistors per longline, available on other XC3000 devices, is not a valid option for XC3100L devices.
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XC3000 Series Field Programmable Gate Arrays XC3100L CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used in the simulator. Speed Grade Symbol 1 8 TILO TCKO TQLO 2 4 6 TICK TDICK TECCK 2.1 1.4 2.7 1.0 0 0.9 0.7 1.6 1.6 270 2.7 3.1 -3 Min Max 2.7 2.1 4.3 1.8 1.3 2.5 1.0 0 0.9 0.7 1.3 1.3 325 2.3 2.7 Min -2 Max 2.2 1.7 3.5 Units ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns 12.0
Description Combinatorial Delay Logic Variables A, B, C, D, E, to outputs X or Y Sequential delay Clock k to outputs X or Y Clock k to outputs X or Y when Q is returned through function generators F or G to drive X or Y Set-up time before clock K Logic Variables A, B, C, D, E Data In DI Enable Clock EC Reset Direct Inactive RD Hold Time after clock K Logic Variables A, B, C, D, E Data In DI Enable Clock EC Clock Clock High time Clock Low time Max. flip-flop toggle rate Reset Direct (RD) RD width delay from RD to outputs X or Y Global Reset (RESET Pad) RESET width (Low) (XC3142L) delay from RESET pad to outputs X or Y
3 5 7 11 12
TCKI TCKDI TCKEC TCH TCL FCLK TRPW TRIO
7
13 9
TMRW TMRQ
12.0
12.0 12.0 Advance
Notes: 1. The CLB K to Q delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data In hold time requirement (TCKDI, #5) of any CLB on the same die. 2. TILO, TQLO and TICK are specified for 4-input functions. For 5-input functions or base FGM functions, each of these specifications for the XC3100L family increase by 0.35 ns (-3) and 0.29 ns (-2).
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XC3000 Series Field Programmable Gate Arrays XC3100L CLB Switching Characteristics Guidelines (continued)
CLB Output (X, Y) (Combinatorial) 1 CLB Input (A,B,C,D,E) 2 CLB Clock 12 TCL 4 CLB Input (Direct In) 6 CLB Input (Enable Clock) 8 CLB Output (Flip-Flop) TCKO T ECCK 7 TCKEC TDICK 11 T CH 5 TCKDI T ICK 3 T CKI T ILO
CLB Input (Reset Direct) 13 TRPW 9 T RIO CLB Output (Flip-Flop)
X5424
T
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XC3000 Series Field Programmable Gate Arrays XC3100L IOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used in the simulator. Speed Grade Symbol 3 TPID TPTG TIKRI TPICK 9.5 9.9 7 7 10 10 9 9 8 8 5 6 11 12 TOKPOTOK
PO
-3 Min Max 2.2 11.0 2.2 Min
-2 Max 2.0 11.0 1.9 Units ns ns ns
Description Propagation Delays (Input) Pad to Direct In (I) Pad to Registered In (Q) with latch (XC3100L) transparent Clock (IK) to Registered In (Q) Set-up Time (Input) Pad to Clock (IK) set-up time XC3142L XC3190L Propagation Delays (Output) Clock (OK) to Pad (fast) same (slew rate limited) Output (O) to Pad (fast) same (slew-rate limited)(XC3100L) 3-state to Pad begin hi-Z (fast) same (slew-rate limited) 3-state to Pad active and valid (fast)(XC3100L) same (slew -rate limited) Set-up and Hold Times (Output) Output (O) to clock (OK) set-up time (XC3100L) Output (O) to clock (OK) hold time Clock Clock High time Clock Low time Export Control Maximum flip-flop toggle rate Global Reset Delays RESET Pad to Registered In (Q) (XC3142L) (XC3190L) (fast) RESET Pad to output pad (slew-rate limited)
4 1
9.0 9.4 4.4 10.0 3.3 9.0 5.5 5.5 9.0 15.0 4.0 9.7 3.0 8.7 5.0 5.0 8.5 14.2 3.6 0 1.3 1.3 325
ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
TOPF TOPF TTSHZ TTSHZ TTSON TTSON TOOK TOKO TIOH TIOL FTOG 4.0 0 1.6 1.6 270
7
13 15 15
TRRI TRPO TRPO
16.0 21.0 17.0 23.0 Advance
16.0 21.0 17.0 23.0
ns ns ns ns
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output
rise/fall times are approximately four times longer. 2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal pull-up resistor or alternatively configured as a driven output or driven from an external source. 3. Input pad set-up time is specified with respect to the internal clock (IK). In order to calculate system set-up time, subtract clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (IK) is negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized.
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XC3000 Series Field Programmable Gate Arrays XC3100L IOB Switching Characteristics Guidelines (continued)
I/O Block (I) 3 I/O Pad Input 1 I/O Clock (IK/OK) 12 TIOL I/O Block (RI) 4 RESET 5 I/O Block (O) 10 TOP I/O Pad Output (Direct) 7 I/O Pad Output (Registered) TOKPO TOOK 6 TOKO 15 TRPO TIKRI 13 TRRI 11 TIOH T PICK T PID
I/O Pad TS 8 I/O Pad Output
X5425
TTSON
9
T TSHZ
Vcc PROGRAM-CONTROLLED MEMORY CELLS
OUT INVERT
3-STATE INVERT
OUTPUT SELECT
SLEW RATE
PASSIVE PULL UP
3- STATE (OUTPUT ENABLE)
T
OUT
O
D
Q
FLIP FLOP
OUTPUT BUFFER
I/O PAD R DIRECT IN REGISTERED IN I Q QD FLIP FLOP or LATCH R OK IK (GLOBAL RESET) TTL or CMOS INPUT THRESHOLD
CK1
CK2 PROGRAM CONTROLLED MULTIPLEXER = PROGRAMMABLE INTERCONNECTION POINT or PIP
X3029
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XC3000 Series Field Programmable Gate Arrays
XC3000 Series Pin Assignments
Xilinx offers the six different array sizes in the XC3000 families in a variety of surface-mount and through-hole package types, with pin counts from 44 to 208. Each chip is offered in several package types to accommodate the available PC board space and manufacturing technology. Most package types are also offered with different chips to accommodate design changes without the need for PC board changes. Note that there is no perfect match between the number of bonding pads on the chip and the number of pins on a package. In some cases, the chip has more pads than there are pins on the package, as indicated by the information ("unused" pads) below the line in the following table. The IOBs of the unconnected pads can still be used as storage elements if the specified propagation delays and set-up times are acceptable. In other cases, the chip has fewer pads than there are pins on the package; therefore, some package pins are not connected (n.c.), as shown above the line in the following table.
XC3000 Series 44-Pin PLCC Pinouts
XC3000A, XC3000L, and XC3100A families have identical pinouts Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 XC3030A GND I/O I/O I/O I/O I/O PWRDWN TCLKIN-I/O I/O I/O I/O VCC I/O I/O I/O M1-RDATA M0-RTRIG M2-I/O HDC-I/O LDC-I/O I/O INIT-I/O Pin No. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 XC3030A GND I/O I/O XTL2(IN)-I/O RESET DONE-PGM I/O XTL1(OUT)-BCLK-I/O I/O I/O I/O VCC I/O I/O I/O DIN-I/O DOUT-I/O CCLK I/O I/O I/O I/O
7
Peripheral mode and Master Parallel mode are not supported in the PC44 package
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XC3000 Series Field Programmable Gate Arrays XC3000 Series 64-Pin Plastic VQFP Pinouts
XC3000A, XC3000L, and XC3100A families have identical pinouts Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 XC3030A A0-WS-I/O A1-CS2-I/O A2-I/O A3-I/O A4-I/O A14-I/O A5-I/O GND A13-I/O A6-I/O A12-I/O A7-I/O A11-I/O A8-I/O A10-I/O A9-I/O PWRDN TCLKIN-I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O M1-RDATA M0-RTRIG Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 XC3030A M2-I/O HDC-I/O I/O LDC-I/O I/O I/O I/O INIT-I/O GND I/O I/O I/O I/O I/O XTAL2(IN)-I/O RESET DONE-PG D7-I/O XTAL1(OUT)-BCLKIN-I/O D6-I/O D5-I/O CS0-I/O D4-I/O VCC D3-I/O CS1-I/O D2-I/O D1-I/O RDY/BUSY-RCLK-I/O D0-DIN-I/O DOUT-I/O CCLK
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XC3000 Series Field Programmable Gate Arrays XC3000 Series 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
68 PLCC XC3030A XC3020A 10 11 12 13 14 -- 15 16 -- 17 18 19 -- 20 -- 21 22 23 24 25 26 27 28 29 30 -- -- 31 32 33 34 35 36 37 38 39 -- -- 40 41 42 43 42 43 32 33 -- 34 35 36 37 38 39 40 41 10 11 -- 12 13 -- 14 15 16 17 18 19 -- 20 21 22 -- 23 24 25 26 27 28 29 30 31 XC3020A, XC3030A, XC3042A PWRDN TCLKIN-I/O I/O* I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O M1-RDATA M0-RTRIG M2-I/O HDC-I/O I/O LDC-I/O I/O I/O* I/O I/O I/O* INIT-I/O GND I/O I/O I/O I/O I/O I/O I/O* I/O* I/O XTL2(IN)-I/O 68 PLCC 84 PLCC 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 XC3030A XC3020A 44 45 46 47 48 -- 49 50 51 -- 52 53 54 55 -- -- 56 57 58 59 60 61 62 63 64 -- -- 65 66 67 68 1 2 3 4 5 -- -- 6 7 8 9 44 45 46 47 48 -- 49 50 51 -- 52 53 54 55 -- -- 56 57 58 59 60 61 62 63 64 -- -- 65 66 67 68 1 2 3 4 5 -- -- 6 7 8 9 XC3020A, XC3030A, XC3042A RESET DONE-PG D7-I/O XTL1(OUT)-BCLKIN-I/O D6-I/O I/O D5-I/O CS0-I/O D4-I/O I/O VCC D3-I/O CS1-I/O D2-I/O I/O I/O* D1-I/O RDY/BUSY-RCLK-I/O D0-DIN-I/O DOUT-I/O CCLK A0-WS-I/O A1-CS2-I/O A2-I/O A3-I/O I/O* I/O* A15-I/O A4-I/O A14-I/O A5-I/O GND A13-I/O A6-I/O A12-I/O A7-I/O I/O* I/O* A11-I/O A8-I/O A10-I/O A9-I/O 84 PLCC 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11
7
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. This table describes the pinouts of three different chips in three different packages. The pin-description column lists 84 of the 118 pads on the XC3042A (and 84 of the 98 pads on the XC3030A) that are connected to the 84 package pins. Ten pads, indicated by an asterisk, do not exist on the XC3020A, which has 74 pads; therefore the corresponding pins on the 84-pin packages have no connections to an XC3020A. Six pads on the XC3020A and 16 pads on the XC3030A, indicated by a dash (--) in the 68 PLCC column, have no connection to the 68 PLCC, but are connected to the 84-pin packages.
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XC3000 Series Field Programmable Gate Arrays XC3064A/XC3090A/XC3195A 84-Pin PLCC Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
PLCC Pin Number 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 XC3064A, XC3090A, XC3195A PWRDN TCLKIN-I/O I/O I/O I/O I/O I/O I/O I/O GND* VCC I/O I/O I/O I/O I/O I/O I/O I/O M1-RDATA M0-RTRIG M2-I/O HDC-I/O I/O LDC-I/O I/O I/O I/O I/O INIT/I/O* VCC* GND I/O I/O I/O I/O I/O I/O I/O I/O I/O XTL2(IN)-I/O PLCC Pin Number 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11 XC3064A, XC3090A, XC3195A RESET DONE-PG D7-I/O XTL1(OUT)-BCLKIN-I/O D6-I/O I/O D5-I/O CS0-I/O D4-I/O I/O VCC GND* D3-I/O* CS1-I/O* D2-I/O* I/O D1-I/O RDY/BUSY-RCLK-I/O D0-DIN-I/O DOUT-I/O CCLK A0-WS-I/O A1-CS2-I/O A2-I/O A3-I/O I/O I/O A15-I/O A4-I/O A14-I/O A5-I/O GND VCC* A13-I/O* A6-I/O* A12-I/O* A7-I/O* I/O A11-I/O A8-I/O A10-I/O A9-I/O
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. * In the PC84 package, XC3064A, XC3090A and XC3195A have additional VCC and GND pins and thus a different pin definition than XC3020A/XC3030A/XC3042A.
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XC3000 Series Field Programmable Gate Arrays XC3000 Series 100-Pin QFP Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Pin No. TQFP PQFP VQFP 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 XC3020A XC3030A XC3042A GND A13-I/O A6-I/O A12-I/O A7-I/O I/O* I/O* A11-I/O A8-I/O A10-I/O A9-I/O VCC* GND* PWRDN TCLKIN-I/O I/O** I/O* I/O* I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O Pin No. TQFP PQFP VQFP 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 XC3020A XC3030A XC3042A I/O* I/O* M1-RD GND* MO-RT VCC* M2-I/O HDC-I/O I/O LDC-I/O I/O* I/O* I/O I/O I/O INIT-I/O GND I/O I/O I/O I/O I/O I/O I/O I/O* I/O* XTL2-I/O GND* RESET VCC* DONE-PG D7-I/O BCLKIN-XTL1-I/O D6-I/O Pin No. TQFP PQFP VQFP 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 XC3020A XC3030A XC3042A I/O* I/O* I/O D5-I/O CS0-I/O D4-I/O I/O VCC D3-I/O CS1-I/O D2-I/O I/O I/O* I/O* D1-I/O RDY/BUSY-RCLK-I/O DO-DIN-I/O DOUT-I/O CCLK VCC* GND* AO-WS-I/O A1-CS2-I/O I/O** A2-I/O A3-I/O I/O* I/O* A15-I/O A4-I/O A14-I/O A5-I/O
7
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. * This table describes the pinouts of three different chips in three different packages. The pin-description column lists 100 of the 118 pads on the XC3042A that are connected to the 100 package pins. Two pads, indicated by double asterisks, do not exist on the XC3030A, which has 98 pads; therefore the corresponding pins have no connections. Twenty-six pads, indicated by single or double asterisks, do not exist on the XC3020A, which has 74 pads; therefore, the corresponding pins have no connections. (See table on page 65.)
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XC3000 Series Field Programmable Gate Arrays XC3000 Series 132-Pin Ceramic and Plastic PGA Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts PGA Pin Number C4 A1 C3 B2 B3 A2 B4 C5 A3 A4 B5 C6 A5 B6 A6 B7 C7 C8 A7 B8 A8 A9 B9 C9 A10 B10 A11 C10 B11 A12 B12 A13 C12 XC3042A XC3064A GND PWRDN I/O-TCLKIN I/O I/O I/O* I/O I/O I/O* I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O* I/O I/O I/O* I/O I/O* I/O PGA Pin Number B13 C11 A14 D12 C13 B14 C14 E12 D13 D14 E13 F12 E14 F13 F14 G13 G14 G12 H12 H14 H13 J14 J13 K14 J12 K13 L14 L13 K12 M14 N14 M13 L12 XC3042A XC3064A M1-RD GND M0-RT VCC M2-I/O HDC-I/O I/O I/O I/O LDC-I/O I/O* I/O I/O I/O I/O I/O INIT-I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O* I/O I/O I/O I/O XTL2(IN)-I/O GND PGA Pin XC3042A Number XC3064A P14 RESET M11 VCC N13 DONE-PG M12 D7-I/O P13 XTL1-I/O-BCLKIN N12 I/O P12 I/O N11 D6-I/O M10 I/O P11 I/O* N10 I/O P10 I/O M9 D5-I/O N9 CS0-I/O P9 I/O* P8 I/O* N8 D4-I/O P7 I/O M8 VCC M7 GND N7 D3-I/O P6 CS1-I/O N6 I/O* P5 I/O* M6 D2-I/O N5 I/O P4 I/O P3 I/O M5 D1-I/O N4 RDY/BUSY-RCLK-I/O P2 I/O N3 I/O N2 D0-DIN-I/O PGA Pin Number M3 P1 M4 L3 M2 N1 M1 K3 L2 L1 K2 J3 K1 J2 J1 H1 H2 H3 G3 G2 G1 F1 F2 E1 F3 E2 D1 D2 E3 C1 B1 C2 D3 XC3042A XC3064A DOUT-I/O CCLK VCC GND A0-WS-I/O A1-CS2-I/O I/O I/O A2-I/O A3-I/O I/O I/O A15-I/O A4-I/O I/O* A14-I/O A5-I/O GND VCC A13-I/O A6-I/O I/O* A12-I/O A7-I/O I/O I/O A11-I/O A8-I/O I/O I/O A10-I/O A9-I/O VCC
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. * Indicates unconnected package pins (14) for the XC3042A.
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XC3000 Series Field Programmable Gate Arrays XC3000 Series 144-Pin Plastic TQFP Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 XC3042A XC3064A XC3090A PWRDN I/O-TCLKIN I/O* I/O I/O I/O* I/O I/O I/O* I/O I/O I/O I/O I/O I/O* I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O* I/O I/O I/O* I/O* I/O I/O* I/O M1-RD GND M0-RT VCC M2-I/O HDC-I/O I/O I/O I/O LDC-I/O I/O* I/O I/O Pin Number 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 XC3042A XC3064A XC3090A I/O I/O* I/O I/O INIT-I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O* I/O* I/O I/O I/O I/O XTL2(IN)-I/O GND RESET VCC DONE-PG D7-I/O XTL1(OUT)-BCLKIN-I/O I/O I/O D6-I/O I/O I/O* I/O I/O I/O* D5-I/O CS0-I/O I/O* I/O* D4-I/O I/O VCC GND D3-I/O CS1-I/O I/O* I/O* D2-I/O Pin Number 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 XC3042A XC3064A XC3090A I/O I/O I/O* I/O I/O* D1-I/O RDY/BUSY-RCLK-I/O I/O I/O D0-DIN-I/O DOUT-I/O CCLK VCC GND A0-WS-I/O A1-CS2-I/O I/O I/O A2-I/O A3-I/O I/O I/O A15-I/O A4-I/O I/O* I/O* A14-I/O A5-I/O I/O (XC3090 only) GND VCC A13-I/O A6-I/O I/O* I/O (XC3090 only) I/O* A12-I/O A7-I/O I/O I/O A11-I/O A8-I/O I/O I/O A10-I/O A9-I/O VCC GND
7
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. * Indicates unconnected package pins (24) for the XC3042A.
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XC3000 Series Field Programmable Gate Arrays XC3000 Series 160-Pin PQFP Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 XC3064A, XC3090A, XC3195A I/O* I/O* I/O* I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O* I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O* I/O* M1-RDATA PQFP Pin Number 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 XC3064A, XC3090A, XC3195A GND M0-RTRIG VCC M2-I/O HDC-I/O I/O I/O I/O LDC-I/O I/O* I/O* I/O I/O I/O I/O I/O I/O I/O INIT-I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O* XTL2-I/O GND RESET VCC DONE/PG PQFP Pin Number 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 XC3064A, XC3090A, XC3195A D7-I/O XTL1-I/O-BCLKIN I/O* I/O I/O D6-I/O I/O I/O I/O I/O I/O D5-I/O CS0-I/O I/O* I/O* I/O I/O D4-I/O I/O VCC GND D3-I/O CS1-I/O I/O I/O I/O* I/O* D2-I/O I/O I/O I/O I/O I/O D1-I/O RDY/BUSY-RCLK-I/O I/O I/O I/O* D0-DIN-I/O DOUT-I/O PQFP Pin Number 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 XC3064A, XC3090A, XC3195A CCLK VCC GND A0-WS-I/O A1-CS2-I/O I/O I/O A2-I/O A3-I/O I/O I/O A15-I/O A4-I/O I/O I/O A14-I/O A5-I/O I/O* GND VCC A13-I/O A6-I/O I/O* I/O* I/O I/O A12-I/O A7-I/O I/O I/O A11-I/O A8-I/O I/O I/O A10-I/O A9-I/O VCC GND PWRDWN TCLKIN-I/O
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed IOBs are default slew-rate limited. * Indicates unconnected package pins (18) for the XC3064A.
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XC3000 Series Field Programmable Gate Arrays XC3000 Series 175-Pin Ceramic and Plastic PGA Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
PGA Pin Number B2 D4 B3 C4 B4 A4 D5 C5 B5 A5 C6 D6 B6 A6 B7 C7 D7 A7 A8 B8 C8 D8 D9 C9 B9 A9 A10 D10 C10 B10 A11 B11 D11 C11 A12 B12 C12 D12 A13 B13 C13 A14 PGA Pin Number D13 B14 C14 B15 D14 C15 E14 B16 D15 C16 D16 F14 E15 E16 F15 F16 G14 G15 G16 H16 H15 H14 J14 J15 J16 K16 K15 K14 L16 L15 M16 M15 L14 N16 P16 N15 R16 M14 P15 N14 R15 P14 PGA Pin Number R14 N13 T14 P13 R13 T13 N12 P12 R12 T12 P11 N11 R11 T11 R10 P10 N10 T10 T9 R9 P9 N9 N8 P8 R8 T8 T7 N7 P7 R7 T6 R6 N6 P6 T5 R5 P5 N5 T4 R4 P4 R3 PGA Pin Number N4 R2 P3 N3 P2 M3 R1 N2 P1 N1 L3 M2 M1 L2 L1 K3 K2 K1 J1 J2 J3 H3 H2 H1 G1 G2 G3 F1 F2 E1 E2 F3 D1 C1 D2 B1 E3 C2 D3 C3
XC3090A, XC3195A PWRDN TCLKIN-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
XC3090A, XC3195A I/O M1-RDATA GND M0-RTRIG VCC M2-I/O HDC-I/O I/O I/O I/O LDC-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O INIT-I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O XTL2(IN)-I/O GND RESET VCC
XC3090A, XC3195A DONE-PG D7-I/O XTL1(OUT)-BCLKIN-I/O I/O I/O I/O I/O D6-I/O I/O I/O I/O I/O I/O D5-I/O CS0-I/O I/O I/O I/O I/O D4-I/O I/O VCC GND D3-I/O CS1-I/O I/O I/O I/O I/O D2-I/O I/O I/O I/O I/O I/O D1-I/O RDY/BUSY-RCLK-I/O I/O I/O I/O I/O D0-DIN-I/O
XC3090A, XC3195A DOUT-I/O CCLK VCC GND A0-WS-I/O A1-CS2-I/O I/O I/O A2-I/O A3-I/O I/O I/O A15-I/O A4-I/O I/O I/O A14-I/O A5-I/O I/O I/O GND VCC A13-I/O A6-I/O I/O I/O I/O I/O A12-I/O A7-I/O I/O I/O A11-I/O A8-I/O I/O I/O A10-I/O A9-I/O VCC GND
7
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. Pins A2, A3, A15, A16, T1, T2, T3, T15 and T16 are not connected. Pin A1 does not exist.
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XC3000 Series Field Programmable Gate Arrays XC3000 Series 176-Pin TQFP Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Number 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Pin Number 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Pin Number 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
XC3090A PWRDWN TCLKIN-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O -
XC3090A M1-RDATA GND M0-RTRIG VCC M2-I/O HDC-I/O I/O I/O I/O LDC-I/O - I/O I/O I/O I/O I/O I/O I/O I/O I/O INIT-I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O - - I/O XTAL2(IN)-I/O GND RESET VCC
XC3090A DONE-PG D7-I/O XTAL1(OUT)-BCLKIN-I/O I/O I/O I/O I/O D6-I/O I/O I/O I/O I/O I/O D5-I/O CS0-I/O I/O I/O I/O I/O D4-I/O I/O VCC GND D3-I/O CS1-I/O I/O I/O I/O I/O D2-I/O I/O I/O I/O I/O I/O D1-I/O RDY/BUSY-RCLK-I/O I/O I/O I/O I/O D0-DIN-I/O DOUT-I/O CCLK
XC3090A VCC GND A0-WS-I/O A1-CS2-I/O - I/O I/O A2-I/O A3-I/O - - I/O I/O A15-I/O A4-I/O I/O I/O A14-I/O A5-I/O I/O I/O GND VCC A13-I/O A6-I/O I/O I/O - - I/O I/O A12-I/O A7-I/O I/O I/O - A11-I/O A8-I/O I/O I/O A10-I/O A9-I/O VCC GND
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited.
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XC3000 Series Field Programmable Gate Arrays XC3000 Series 208-Pin PQFP Pinouts
XC3000A, and XC3000L families have identical pinouts
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 XC3090A - GND PWRDWN TCLKIN-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O - I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O - I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O M1-RDATA GND M0-RTRIG - - Pin Number 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 XC3090A - - VCC M2-I/O HDC-I/O I/O I/O I/O LDC-I/O I/O I/O - - - - I/O I/O I/O I/O - - I/O I/O I/O INIT-I/O VCC GND I/O I/O I/O - - I/O I/O I/O I/O I/O - - - I/O I/O I/O I/O I/O I/O I/O XTL2-I/O GND RESET - - Pin Number 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 XC3090A - VCC D/P - D7-I/O XTL1-BCLKIN-I/O I/O I/O I/O I/O D6-I/O I/O I/O I/O - I/O I/O D5-I/O CS0-I/O I/O I/O I/O I/O D4-I/O I/O VCC GND D3-I/O CS1-I/O I/O I/O I/O I/O D2-I/O I/O I/O I/O - I/O I/O D1-I/O RDY/BUSY-RCLK-I/O I/O I/O I/O I/O DIN-D0-I/O DOUT-I/O CCLK VCC - - Pin Number 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 XC3090A - - - GND WS-A0-I/O CS2-A1-I/O I/O I/O A2-I/O A3-I/O I/O I/O - - - A15-I/O A4-I/O I/O I/O - - A14-I/O A5-I/O I/O I/O GND VCC A13-I/O A6-I/O I/O I/O - - I/O I/O A12-I/O A7-I/O - - - I/O I/O A11-I/O A8-I/O I/O I/O A10-I/O A9-I/O VCC - - -
7
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. * In PQ208, XC3090A and XC3195A have different pinouts.
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XC3000 Series Field Programmable Gate Arrays XC3195A PQ208 Pinouts
Pin Description A9-I/O A10-I/O I/O I/O I/O I/O A8-I/O A11-I/O I/O I/O I/O I/O A7-I/O A12-I/O I/O I/O I/O I/O I/O I/O A6-I/O A13-I/O VCC GND I/O I/O A5-I/O A14-I/O I/O I/O I/O I/O A4-I/O A15-I/O I/O I/O I/O I/O A3-I/O A2-I/O I/O I/O I/O I/O A1-CS2-I/O A0-WS-I/O GND VCC CCLK DOUT-I/O
PQ208 206 205 204 203 202 201 200 199 198 197 196 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155
Pin Description D0-DIN-I/O I/O I/O I/O I/O
RDY/BUSY-RCLK-I/O
PQ208 154 153 152 151 150 149 148 147 146 145 144 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
Pin Description I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC INIT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O LDC-I/O I/O I/O I/O HDC-I/O M2-I/O VCC M0-RTIG GND M1/RDATA I/O
PQ208 102 101 100 99 98 97 96 95 94 93 92 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
Pin Description I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCLKIN-I/O PWRDN
GND VCC
PQ208 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 14 13 12 11 10 9 8 7 6 5 4 3 2 1
208 207
D1-I/O I/O I/O I/O I/O I/O I/O I/O D2-I/O I/O I/O I/O I/O CS1-I/O D3-I/O GND VCC I/O D4-I/O I/O I/O I/O I/O CS0-I/O D5-I/O I/O I/O I/O I/O I/O I/O I/O D6-I/O I/O I/O I/O I/O
XTLX1(OUT)BCLKN-I/O
D7-I/O D/P VCC RESET GND XTL2(IN)-I/O
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. In the PQ208 package, pins 15, 16, 64, 65, 90, 91, 142, 143, 170 and 195 are not connected. * In PQ208, XC3090A and XC3195A have different pinouts.
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XC3000 Series Field Programmable Gate Arrays
Product Availability
Pins 44 Plast. PLCC PC44 64 Plast. VQFP VQ64 68 Plast. PLCC PC68 Plast. PLCC PC84 84 Cer. PGA PG84 Plast. PQFP PQ100 100 Plast. TQFP TQ100 Plast. VQFP VQ100 132 Plast. PGA PP132 Cer. PGA PG132 144 Plast. TQFP TQ144 160 Plast. PQFP PQ160 175 Plast. PGA PP175 Cer. PGA PG175 176 Plast. TQFP TQ176 208 Plast. PQFP PQ208 Type Code
XC3020A XC3030A XC3042A XC3064A XC3090A XC3020L XC3030L XC3042L XC3064L XC3090L
-7 -6 -7 -6 -7 -6 -7 -6 -7 -6 -8 -8 -8 -8 -8 -4 -3 CI CI C CI C
CI C CI C
CI C CI C CI C CI C CI C CI CI CI CI CI CI C
CI C CI C CI C CI C CI C CI C CI C CI C CI C CI C CI C CI CI CI CI CI CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C C CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C CI CI C CI C CI C CI C CI C CI C
CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C
CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C
XC3120A
-2 -1 -09 -4 -3 -2 -1 -09 -4 -3
XC3130A
7
XC3142A
-2 -1 -09 -4 -3 -2 -1 -09 -4 -3 -2 -1 -09 -4 -3
XC3164A
XC3190A
XC3195A
-2 -1 -09
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XC3000 Series Field Programmable Gate Arrays
Pins 44 Plast. PLCC PC44 64 Plast. VQFP VQ64 68 Plast. PLCC PC68 Plast. PLCC PC84 84 Cer. PGA PG84 Plast. PQFP PQ100 100 Plast. TQFP TQ100 Plast. VQFP VQ100 132 Plast. PGA PP132 Cer. PGA PG132 144 Plast. TQFP TQ144 160 Plast. PQFP PQ160 175 Plast. PGA PP175 Cer. PGA PG175 176 Plast. TQFP TQ176 208 Plast. PQFP PQ208
Type Code
XC3142L XC3190L Notes:
C C C C C = Commercial, TJ= 0 to +85C
C C
C C C C C C
I = Industrial, TJ = -40 to +100C
Number of Available I/O Pins
Max I/O 64 80 96 120 144 176 44 34 64 54 68 58 58 84 64 74 74 70 70 70 Number of Package Pins 100 132 144 160 64 80 82 96 96 110 120 120 122 138 138 175 176 208
XC3020A/XC3120A XC3030A/XC3130A XC3042A/3142A XC2064A/XC3164A XC3090A/XC3190A XC3195A
144 144
144
144 176
Ordering Information
Example: Device Type Speed Grade
XC3030A-3 PC44C Temperature Range Number of Pins Package Type
Revision History Date 11/98 Revision Revised version number to 3.1, removed XC3100A-5 obsolete packages.
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